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automotive power data sheet rev. 1.0, 2016-05-06 TLE9843QX microcontroller with lin and power s witches for automotive applications
TLE9843QX table of contents data sheet 2 rev. 1.0, 2016-05-06 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 device pinout and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.2 pmu modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 power supply generation (pgu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.1 voltage regulator 5.0v (vddp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.2 voltage regulator 1.5v (vddc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.3 external voltage regulator 5.0v (vddext) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.4 power-on reset concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 system control unit - digital modules (scu-dm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3 clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.1 low precision clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.2 high precision oscillator circuit (osc_hp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.2.1 external input clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.2.2 external crystal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.3 clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 system control unit - power modules (scu-pm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 description of the power modules system control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 arm cortex-m0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 address space organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 memory control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11 nvm module (flash memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.1.1 general definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table of contents
TLE9843QX table of contents data sheet 3 rev. 1.0, 2016-05-06 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13 watchdog timer (wdt1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 14 gpio ports and peripheral i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.2.1 port 0 and port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14.2.2 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 14.3 TLE9843QX port implementation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.3.1 port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.3.1.1 port 0 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.3.2 port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.3.2.1 port 1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.3.3 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.3.3.1 port 2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15 general purpose timer units (gpt12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.1.1 features block gpt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.1.2 features block gpt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.2.1 block diagram gpt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15.2.2 block diagram gpt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 16 timer2 and timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 16.2.1 timer2 and timer21 modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17 capture/compare unit 6 (ccu6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.1 feature set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 18 uart1/uart2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 18.3 uart modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 19 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 19.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 20 high-speed synchronous serial interface ssc1/ssc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 20.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 21 measurement unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 21.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
TLE9843QX table of contents data sheet 4 rev. 1.0, 2016-05-06 21.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 22 measurement core module (incl. adc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 22.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 22.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 23 10-bit analog digital converter (adc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 23.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 23.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 24 high-voltage monitor input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 24.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 24.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 25 high-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 25.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 25.2.2 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 26 low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 26.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 26.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 27 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 27.1 relay window lift application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 27.2 connection of n.c. / n.u. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 27.3 connection of unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 27.4 connection of p0.2 for swd debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 27.5 connection of tms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 27.6 esd immunity according to iec61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 28 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 28.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 28.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 28.1.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 28.1.3 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 28.1.4 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 28.1.5 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 28.2 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 28.2.1 pmu input voltage vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 28.2.2 pmu i/o supply parameters vddp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 28.2.3 pmu core supply parameters vddc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 28.2.4 vddext voltage regulator 5.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 28.2.5 vpre voltage regulator (pmu subblock) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 28.2.5.1 load sharing of vpre regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 28.2.6 power down voltage regulator (pmu subblock) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 28.3 system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 28.3.1 electrical characteristics oscillators and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 28.3.2 external clock parameters xtal1, xtal2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 28.4 flash parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 28.4.1 flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
TLE9843QX table of contents data sheet 5 rev. 1.0, 2016-05-06 28.5 parallel ports (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 28.5.1 description of keep and force current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 28.5.2 dc parameters port 0, port 1, tms, reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 28.5.3 dc parameters port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 28.5.4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 28.6 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 28.6.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 28.7 high-speed synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 28.7.1 ssc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 28.8 measurement unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 28.8.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 28.8.2 central temperature sensor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 28.8.2.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 28.9 adc1 (10-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 28.9.1 adc1 reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 28.9.2 electrical characteristics adc1 (10-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 28.10 high-voltage monitoring input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 28.10.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 28.11 high side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 28.11.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 28.12 low side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 28.12.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 29 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 26 30 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
vqfn-48-31 type package marking TLE9843QX vqfn-48-31 TLE9843QX data sheet 6 rev. 1.0, 2016-05-06 microcontroller with li n and power switches for automotive applications TLE9843QX 1overview summary of features ? 32-bit arm cortex-m0 core ?up to 25 mhz clock frequency ? one clock per machine cycle architecture ? single cycle multiplier ? on-chip memory ? 48 kb flash (including eeprom) ? 4 kb eeprom (emulated in flash) ? 768 bytes 100 time programmable memory (100tp) ?4 kb ram ? boot rom for startup firmware and flash routines ?on-chip osc ? 2 low-side switches incl. pwm functiona lity, can be used e.g. as relay driver ? 1 high-side switch with cyclic sense option and pwm fu nctionality, e.g. for supply ing leds or switch panels (min. 150 ma) ? 4 high voltage monitor input pins for wake-up a nd with cyclic sense with analog measurement option ? 10 general-purpose i/o ports (gpio) ? 6 analog input ports ? 10-bit a/d converter with 6 analog inputs + vbat_sense + vs + 4 high voltage monitoring inputs ? 8-bit a/d converter with 7 inputs for voltage and temperature supervision ? measurement unit with 12 channels together with t he onboard 10-bit a/d converter and data post processing ? 16-bit timers - gpt12, timer 2 and timer 21 ? capture/compare unit for pwm signal generation (ccu6) ? 2 full duplex serial interfaces (u art1, uart2), uart1 with lin support ? 2 synchronous serial channels (ssc1, ssc2) ? on-chip debug support via 2-wire swd ? lin bootstrap loader to program the flash via lin (lin bsl) ? 1 lin 2.2 transceiver ? single power supply from 3.0 v to 28 v ? low-dropout voltage regulators (ldo) ? 5 v voltage supply vddext for ex ternal loads (e.g. hall-sensor) ? core logic supply at 1.5 v ? programmable window watchdog (wdt1) with independent on-chip clock source ? power saving modes: ? micro controller unit slow-down mode
TLE9843QX overview data sheet 7 rev. 1.0, 2016-05-06 ? sleep mode with cyclic sense option ? cyclic wake-up during sleep mode ? stop mode with cyclic sense option ? power-on and undervoltage/brownout reset generator ? overtemperature protection ? short circuit protection for all voltage re gulators and actuators (high side, low side) ? loss of clock detection with fa il safe mode for power switches ? temperature range t j : -40 c up to 150 c ? package vqfn-48-31 with lti feature ? green package (rohs compliant) ? aec qualified
TLE9843QX overview data sheet 8 rev. 1.0, 2016-05-06 1.1 abbreviations the following acronyms and terms are used within this document. list see in table 1 . table 1 acronyms acronyms name ahb arm advanced high-performance bus ccu6 capture compare unit 6 cgu clock generation unit clkmu clock management unit cmu cyclic management unit dpp data post processing ecc error correction code eeprom electrically erasable pr ogrammable read only memory gpio general purpose input output hv high voltage icu interrupt control unit ldo low dropout voltage regulator lin local interconnect network lsb least significant bit lti lead tip inspection lv low voltage mcu microcontroller unit mf measurement functions mpu memory protection unit mrst master receive / slave transm it, corresponds to miso in spi msb most significant bit mtsr master transmit / slave receiv e, corresponds to mosi in spi mu measurement unit nmi non maskable interrupt nvic nested vector interrupt controller osc oscillator otp one time programmable pba peripheral bridge pc program counter pcu power control unit pd pull down pgu power supply generation unit pll phase locked loop pmu power management unit ppb private peripheral bus
TLE9843QX overview data sheet 9 rev. 1.0, 2016-05-06 psw program status word pu pull up pwm pulse width modulation ram random access memory rcu reset control unit rfu reserved for future use rmu reset management unit rom read only memory scu system control unit sow short open window (for wdt1) spi serial peripheral interface ssc synchronous serial channel swd arm serial wire debug tccr temperature compensation control register tms test mode select tsd thermal shut down uart universal asynchronous receiver transmitter vbg voltage reference band gap vco voltage controlled oscillator wdt1 watchdog timer in scu-pm (sys tem control unit - power modules) wmu wake-up management unit 100tp 100 times programmable table 1 acronyms acronyms name
TLE9843QX block diagram data sheet 10 rev. 1.0, 2016-05-06 2 block diagram figure 1 block diagram, TLE9843QX test / debug interface arm cortex-m0 flash sram rom multilayer ahb matrix pba0 adc10b ls1 pmu ? power management unit 1- 4 mon pba1 uart1 ssc1 t21 scu_dm pll gpio p0.x p1.x p2.x (anx) mon 1...4 mu: dpp2 lin vddc vddp vddext reset vs gndlin lin systembus slave slave slave slave slave ls1 p0.0 tms ccu6 ls2 ls2 gndls hs1 hs1 uart2 ssc2 gpt12 p2.x dpp1 t2 adc8b scu_pm wdt1 vbat_sense
TLE9843QX device pinout and pin configuration data sheet 11 rev. 1.0, 2016-05-06 3 device pinout and pin configuration 3.1 device pinout figure 2 device pinout, TLE9843QX e p2.1 37 13 gndls 24 p0.4 25 p0.5 36 p2.3 e e e ls 1 1 1 n.c. 10 n.u. 9 mo n4 8 mo n3 7 mo n2 6 mo n1 5 n.u. 4 hs1 3 gndlin 2 li n 1 14 p1.0 15 p1.1 16 p1.2 17 p0.1 18 tms / swd _io 19 gndp 20 p0.0 / swd _clk 21 reset 22 p0.2 23 p0.3 26 p1.4 27 n . c. 28 n . c. 29 n . c. 30 gn d p 31 p2.5 / xtal2 32 p2.4 / xtal1 33 p2.2 34 p2.6 35 p2.7 n.c. 38 ls 2 1 2 p2.0 39 n.c. 40 n.c. 41 vddc 42 gnda 43 vddp 4 4 vddext 4 5 n.c. 46 vs 4 7 vbat _ sense 4 8
TLE9843QX device pinout and pin configuration data sheet 12 rev. 1.0, 2016-05-06 3.2 pin configuration after reset, all pins are configured as input (except supply and lin pins) with one of the following settings: ? pull-up enabled only (pu) ? pull-down enabled only (pd) ? input with both pull-up and pull-down disabled (i) ? output with output stage deacti vated = high impedance state (hi-z) the functions and default states of the TLE9843QX external pins are provided in the following table. type: indicates the pin type. ? i/o: input or output ? i: input only ? o: output only ? p: power supply not all alternate functions listed, see chapter 14 . table 2 pin definitions and functions symbol pin number type reset state function p0 port 0 port 0 is an 6-bit bidirectional general purpose i/o port. alternate functions c an be assigned and are listed in the port description. main function is listed below. p0.0 20 i/o i/pu swd_clk gpio serial wire debug clock general purpose io alternate function mapping see table 8 p0.1 17 i/o i/pu gpio general purpose io alternate function mapping see table 8 p0.2 22 i/o i/pd gpio general purpose io alternate function mapping see table 8 p0.3 23 i/o i/pu gpio general purpose io alternate function mapping see table 8 p0.4 24 i/o i/pu gpio general purpose io alternate function mapping see table 8 p0.5 25 i/o i/pu gpio general purpose io alternate function mapping see table 8 p1 port 1 port 1 is an 4-bit bidirectional general purpose i/o port. alternate functions c an be assigned and are listed in the port description. main function is listed below. p1.0 14 i/o i gpio general purpose io alternate function mapping see table 9 p1.1 15 i/o i gpio general purpose io alternate function mapping see table 9 p1.2 16 i/o i gpio general purpose io alternate function mapping see table 9 p1.4 26 i/o i gpio general purpose io alternate function mapping see table 9
TLE9843QX device pinout and pin configuration data sheet 13 rev. 1.0, 2016-05-06 p2 port 2 port 2 is an 8-bit general purpose input-only port. alternate functions c an be assigned and are listed in the port description. main function is listed below. p2.0 39 i i an0 adc1 analog input channel 12 alternate function mapping see table 10 p2.1 37 i i an1 adc1 analog input channel 7 alternate function mapping see table 10 p2.2 33 i i an2 adc1 analog input channel 8 alternate function mapping see table 10 p2.3 36 i i an3 adc1 analog input channel 9 alternate function mapping see table 10 p2.4 32 i i xtal1 1) alternate function mapping see table 10 external oscillator input p2.5 31 i o i hi-z xtal2 1) alternate function mapping see table 10 external oscillator output p2.6 34 i i an6 adc1 analog input channel 10 alternate function mapping see table 10 p2.7 35 i i an7 adc1 analog input channel 11 alternate function mapping see table 10 power supply vs 47 p ? battery supply input vddp 44 p ? i/o port supply (5.0 v). do not connect external loads. for buffer and bypass capacitors. vddc 42 p ? core supply (1.5 v during active mode, 0.9 v during stop mode). do not connect external loads. for buffer/bypass capacitor. vddext 45 p ? external voltage supply output (5.0 v, 20 ma) gndls 13 p ? low-side ground ls1, ls2 gndp 19, 30 p ? core supply ground gnda 43 p ? analog supply ground gndlin 2 p ? lin ground monitor inputs mon1 5 i i high voltage monitor input 1 mon2 6 i i high voltage monitor input 2 mon3 7 i i high voltage monitor input 3 mon4 8 i i high voltage monitor input 4 high-side switch / low- side switch outputs ls1 11 o hi-z low-side switch output 1 ls2 12 o hi-z low-side switch output 2 table 2 pin definitions and functions (cont?d) symbol pin number type reset state function
TLE9843QX device pinout and pin configuration data sheet 14 rev. 1.0, 2016-05-06 hs1 3 o hi-z high-side switch output 1 lin interface lin 1 i/o pu lin bus interface input/output others tms 18 i i/pd tms swd_io test mode select input serial wire debug input/output reset 21 i/o i/o/pu reset input/output, not available during sleep mode vbat_sense 48 i i battery supply voltage sense input n.c. 10, 27, 28, 29, 38, 40, 41, 46 ? ? not connected, can be connected to gnd n.u. 4, 9 ? ? not used; see chapter 27.2 ep ? ? ? exposed pad, connect to gnd 1) configurable by user table 2 pin definitions and functions (cont?d) symbol pin number type reset state function
TLE9843QX modes of operation data sheet 15 rev. 1.0, 2016-05-06 4 modes of operation this highly integrated circuit contains analog and digital functional blocks. for system and interface control an embedded 32-bit cortex-m0 microcontroller is included. fo r internal and external power supply purposes, on-chip low drop-out regulators are existent. an internal o scillator (no external components necessary) provides a cost effective and suitable clock in particular for lin slave nodes. as communication interface, a lin transceiver and several high voltage monitor inputs with adjustable th reshold and filters are ava ilable. furthermore onehigh- sides switche (e.g. for driving leds or powering of switch es), two low-side switches (e.g. for relays) and several general purpose input/outputs (gp io) with pulse-width modulation (pwm) capabilities are available. the micro controller unit supervision and system prot ection including reset feature is controlled by a programmable window watchdog. a cyclic wake-up circuit, supply voltage supervision and integrated temperature sensors are available on-chip. all relevant modules offer power saving modes in order to support terminal 30 connec ted automotive applications. a wake-up from the power saving mode is possible via a li n bus message, via the monitoring inputs or repetitive with a programmable time period (cyclic wake-up). the integrated circuit is available in a package with 0.5 mm pitch and is designed to withstand the challenging conditions of automotive applications. the TLE9843QX has several operational modes mainly to support low power consumption requirements. the low power modes and state transitions are depicted in figure 3 below. figure 3 power control state diagram safety fallback sleep command sleep mode active mode stop mode stop command transition by software transition by external event lin wake or mon wake lin wake or mon wake or gpio wake power-up vs > 3v cyclic-sense cyclic wake cyclic wake vddc stable & error_supp < 5 vddc fail (error_supp++) wdt1 reset (error_wdt++) safety fallback error_supp = 5 safety fallback error_wdt = 5 transition by internal event cyclic-sense reset pmu_system_modes.vsd
TLE9843QX modes of operation data sheet 16 rev. 1.0, 2016-05-06 reset mode the reset mode is a transition mode e.g. during power-up of the device after a power- on reset. in this mode the on-chip power supplies are enabled and all other modules are initialized. once the co re supply vddc is stable, the active mode is entered. in case the watchdog timer wd t1 fails for more than four times, a fail-safe transition to the sleep mode is done. active mode in active mode all module s are activated and the tle9 843qx is fully operational. stop mode the stop mode is one out of two major low power modes. the transition to the low power modes is done by setting the respective bits in the mode c ontrol register. in stop mode the embedded micr ocontroller is still powered allowing faster wake-up reaction times, but not clocked. a wake-up from this mode is possible by lin bus activity, the high voltage monitor input pins or the respective 5v gpios. sleep mode the sleep mode is a major low-power mode. the transiti on to the low-power modes is done by setting the respective bits in the micro controlle r unit mode control register. the sle ep time is configurable. in sleep mode the embedded microcontroller power supply is deactivate d, allowing the lowest system power consumption, but the wake-up time is longer compared to the stop mode. in this mode a 64 bit wide buffer for data storage is available. a wake-up from this mode is possible by li n bus activity or the high voltage monitor input pins and cyclic wake. a wake-up from sleep mo de behaves similar to a power-on reset. while changing into sleep mode, no incoming wake-requests are lost (i.e. no dead-time). it is possible to enter sleep -mode even with lin dominant. cyclic wake-up mode the cyclic wake-up mode is a special operating mode of the sleep mode and the stop mode. the transition to the cyclic wake-up mode is done by first setting the respective bits in the mode control register followed by the sleep or stop command. additional to the cyclic wake-up be havior (wake-up after a programmable time period), the wake-up sources of the normal stop mode and sleep mode are available. cyclic sense mode the cyclic sense mode is a special operating mode of th e sleep mode and the stop mode. the transition to the cyclic sense mode is done by first setti ng the respective bits in the mode c ontrol register followed by the stop or sleep command. in cyclic sense mode the high-side switch can be swit ched on periodically for biasing some switches for example. the wake-up condition is configur able, when the sense result of defined monitor inputs at a window of interest changed compared to the previous wake-up period or reached a defined state respectively. in this case the active mode is entered immediately. the following table shows the possible power mode configur ations of each major module or function respectively. table 3 power mode configurations module/function active mode sleep mode stop mode comment vpre, vddp, vddc on off on ? vddext on/off off cyclic on/off ? hsx on/off cyclic on/off cyclic on/off cyclic sense lsx on/off off off ? lin trx on/off wake-up only / off wake-up only/ off ?
TLE9843QX modes of operation data sheet 17 rev. 1.0, 2016-05-06 wake-up source prioritization all wake-up sources have the same priority. in order to handle the asynchronous nature of the wake-up sources, the first wake-up signal will in itiate the wake-up se quence. nevertheless all wake-up sources are latched in order to provide all wake-up events to the application software. the software can clear the wake-up source flags. it is ensured, that no wake-up event is lost. as default wake-up sources, mon inputs and cyclic wake are activated after power-on reset, lin is disabled as wake-up source by default . wake-up levels and transitions the wake-up can be triggere d by rising, falling or both signal edge s for each monitor input individually. monx (wake-up) n.a. disabled/static/ cyclic disabled/static/ cyclic cyclic: combined with hs=on monx (measurement) on/off off off available on all channels vs sense on/off brownout detection brownout detection brownout detection brownout det. done in pcu vbat_sense on/off off off ? gpio 5v on off on ? wdt1 on off off ? cyclic wake n.a. cyclic wake-up/ cyclic sense/off cyclic wake-up/ cyclic sense/off cyclic sense with hs; wake-up needs mc for enter sleep mode again measurement on 1) off off ? micro controller unit on/slow- down/stop off off ? clock gen (mc) on off off ? lp_clk ( f lp_clk )onoff off wdt1 lp_clk2 ( f lp_clk2 ) on on on for cyclic wake-up 1) may not be switched off due to safety reasons table 3 power mode configurations (cont?d) module/function active mode sleep mode stop mode comment
TLE9843QX power management unit (pmu) data sheet 18 rev. 1.0, 2016-05-06 5 power management unit (pmu) 5.1 features ? system modes control (startup, sleep, stop and active) ? power management (cyclic wake) ? control of system voltage re gulators with diagnosis (overload, short, overvoltage) ? fail safe mode detection and operation in case of system errors (watchdog fail) ? wake-up sources configuration and management (lin, mon, gpios) ? system error logging 5.2 introduction the purpose of the power management unit is to ensure the fail safe behavior of the system ic. therefore the power management unit controls all system modes including the corresponding transitions. the power management unit is responsible for generating all needed voltage supplies for the embedded mcu (vddc, vddp) and the external supply (vddext). additionally, the pmu provides well defined sequences for the system mode transitions and generates hierarch ical reset priorities. the reset priori ties control the reset behavior of all system functionalities especially the reset behavior of the embedded mcu. all thes e functions are controlled by finite state machines. the system mast er functionality of the pmu requires th e generation of an independent logic supply and system clock. therefore the pmu has a module internal logic supply a nd system clock which works independently of the mcu clock.
TLE9843QX power management unit (pmu) data sheet 19 rev. 1.0, 2016-05-06 5.2.1 block diagram the following figure shows the structure of the power management unit. table 4 describes the submodules more detailed. figure 4 power management unit block diagram table 4 description of pmu submodules mod. name modules functions power down supply independent supply voltage generation for pmu this supply is dedicated to the pmu to ensure an independent operation from generated power supplies (vddp, vddc). lp_clk (= f lp_clk ) - clock source for all pmu submodules - backup clock source for system - clock source for wdt1 this ultra low power oscillato r generates the clock for the pmu. this clock is also used as backup clock for the system in case of pll clock failure and as independent clock source for wdt1. lp_clk2 (= f lp_clk2 ) clock source for pmu this ultra low power oscillator generates the clock for the pmu in stop mode and in the cyclic modes. peripherals peripheral blocks of pmu these blocks include the a nalog peripherals to ensure a stable and fail safe pmu startup and operation (bandgap, bias). power_ management.vsd power down supply lp_clk lp_clk2 peripherals power supply generation unit (pgu) ldo for external supply vddext pmu-wmu lin monx pmu-pcu pmu-sfr pmu-rmu pmu-cmu e.g. for wdt 1 e.g. for cyclic wake vs vddp vddc vddext power management unit pmu-control i n t e r n a l b u s
TLE9843QX power management unit (pmu) data sheet 20 rev. 1.0, 2016-05-06 power supply generation unit (pgu) voltage regulators for vddp and vddc this block includes the voltage regulators for the pad supply (vddp) and the core supply (vddc). vddext voltage regula tor for vddext to supply external modules (e.g. sensors) this voltage regulator is a dedicated supply for external modules. pmu-sfr all pmu relevant extended special function registers this module contains all pmu relevant registers, which are needed to control and monitor the pmu. pmu-pcu power control unit of the pmu this block is responsible for cont rolling all power related actions within the pgu module.it also contains all regulator related diagnosis like under- and overvoltage detection, overcurrent and short circuit diagnoses. pmu-wmu wake-up management unit of the pmu this block is responsible for controlling all wake-up related actions within the pmu module. pmu-cmu cyclic management unit of the pmu this bloc k is responsible for controlling all actions within cyclic mode. pmu-rmu reset management unit of the pmu this bl ock generates resets triggered by the pmu like undervoltage or short circuit reset, and passes all resets to the relevant modules and their register. a reset status register with every reset source is available. table 4 description of pmu submodules (cont?d) mod. name modules functions
TLE9843QX power management unit (pmu) data sheet 21 rev. 1.0, 2016-05-06 5.2.2 pmu modes overview the following state diagram shows the available modes of the device. figure 5 power management unit system modes start-up active stop sleep stop command (from mcu) lin-wake or mon-wake or gpio-wake or cyclic _wake or pmu_pin = 1 or sup_tmout = 1 vddc =stable and error_supp<5 error_sup=5 pmu_system _ modes _cus_ w_stopp .vsd v s > 4v and v s ramp up or v s < 3v and v s ramp down lin-wake or mon-wake or cyclic -wake vddc / vddp = fail (short circuit ) ? error_supp ++ sleep command (from mcu ) or wdt1_seq_fail = 1 ( ? error_wdt = 5) or vddc / vddp = overload pmu_pin = 1 or pmu_soft = 1 or (pmu_ext_wdt = 1 and wdt1_seq_fail = 0 ? error_wdt ++) cyclic sense cyclic sense
TLE9843QX power management unit (pmu) data sheet 22 rev. 1.0, 2016-05-06 5.3 power supply generation (pgu) 5.3.1 voltage regulator 5.0v (vddp) this module represents the 5 v voltage regulator, which pr ovides the pad supply for the parallel port pins and other 5 v analog functions (e.g. lin transceiver). features ? 5 v low-drop voltage regulator ? overcurrent monitoring and shutdown with mcu signalling (interrupt) ? overvoltage monitoring with mcu signalling (interrupt) ? undervoltage monitoring with mcu signalling (interrupt) ? undervoltage monitoring with reset (undervoltage reset, v ddpuv ) ? overtemperature shutdown wit h mcu signallin g (interrupt) ? pre-regulator for vddc regulator ? gpio supply ? pull down current source at the output for sleep mode only (typ.5 ma) the output capacitor c vddp is mandatory to ensure a proper regulator functionality. figure 6 module block diagram of vddp voltage regulator ldo_block_external .vsd 5v ldo ldo supervision vs supp_short pmu_5v_overvolt vddp regulator v i a vpre vddp c vddp gnd pmu_5v_overload (overcurr)
TLE9843QX power management unit (pmu) data sheet 23 rev. 1.0, 2016-05-06 5.3.2 voltage regulator 1.5v (vddc) this module represents the 1.5 v voltag e regulator, which provides the supply for the microcontroller core, digital peripherals and other chip internal analog 1.5 v functions (e.g. adc). features ? 1.5 v low-drop vo ltage regulator ? overcurrent monitoring and shut down with mcu signalling (interrupt) ? overvoltage monitoring with mcu signalling (interrupt) ? undervoltage monitoring with mcu signalling (interrupt) ? undervoltage monitoring with reset ? overtemperature shutdown wi th mcu signalling (interrupt) ? pull down current source at the output for sleep mode only (typ. 100 a) the output capacitor c vddc is mandatory to ensure a pr oper regulator functionality. figure 7 module block diagram of vddc voltage regulator 1.5vldoblockexternal.vsd 1.5v ldo vddc (1.5v) supervision vddp (5v) pmu_1v5_overload pmu_1v5_overvolt pmu_1v5_overcurr c vddp c vddc vddc regulator a i v v
TLE9843QX power management unit (pmu) data sheet 24 rev. 1.0, 2016-05-06 5.3.3 external voltage re gulator 5.0v (vddext) this module represents the 5 v voltage regulator, which serves as a supply for extern al circuits. it can be used e.g. to supply an external sensor, leds or potentiometers. features ? switchable (by software) +5 v, low-drop voltage regulator ? switch-on undervoltage blanking time in order to drive small capacitive loads ? intrinsic current limitation ? undervoltage monitoring an d shutdown with mcu signalling (interrupt) ? overtemperature shutdown wi th mcu signalling (interrupt) ? pull down current source at the output for sleep mode only (typ. 100 a) ? cyclic sense option together with gpios ? low current mode available to ensure reduced stop mode current consumption. in this mode current capability is reduced to i vddext_lcm the output capacitor c vddext is mandatory to ensure a proper regulator functionality. figure 8 module block diagram hall_ ldoblockexternal. vsd vddext ldo vddext (5v) supervision vs vddext_undervolt vddext_overtemp c vs c vddext vddext regulator v v
TLE9843QX power management unit (pmu) data sheet 25 rev. 1.0, 2016-05-06 5.3.4 power-on reset concept figure 9 power-on reset concept vs 1.5v pmu _1v5didpor 5v vddp 3v system_state active down lp_clk 1.5v vddc 80h xxh pmu _rst_sts reset _pin start-up fail stable supply_status ok ca. 4v ca. 3.5v
TLE9843QX system control unit - digital modules (scu-dm) data sheet 26 rev. 1.0, 2016-05-06 6 system control unit - digital modules (scu-dm) 6.1 features ? flexible clock conf iguration features ? reset management of all system resets ? system modes control for all power modes (active, power down, sleep) ? interrupt enabling for many system peripherals ? general purpose input output control ? debug mode control of system peripherals 6.2 introduction the system control unit (scu) supports all central cont rol tasks in the TLE9843QX. th e scu is made up of the following sub-modules: ? clock system and control (cgu) ? reset control (rcu) ? power management (pcu) ? interrupt management (icu) ? general port control ? flexible peripheral management ? module suspend control ? error detection and corr ection in data memory ? miscellaneous control ? register mapping
TLE9843QX system control unit - digital modules (scu-dm) data sheet 27 rev. 1.0, 2016-05-06 6.2.1 block diagram figure 10 system control unit - digital modules block diagram io description of scu_dm: ?cgu: ? f sys ; system clock ? lp_clk; low-power backup clock ?rcu: ? 1v5didpor; undervoltage reset of power down supply ? pmu_pin; reset generated by reset pin ? pmu_extwdt; wdt1 reset ? pmu_soft; software reset ? pmu_wake; stop mode exit with reset ? reset_type_3; peripheral reset (contains all resets) scu_dm_block_diagram_ cust.vsd system control unit -digital modules pcu amba ahb on signals to digital peripherals; status signals from digital peripherals cgu fsys lp_clk icu i n t e r n a l b u s nmi intisr <9:0> rcu pmu_1v5didpor baudrate generator / lin frame detection fbr port control p0_pocony.pdmx misc control modpiselx pmu_pin pmu_extwdt pmu_soft pmu_wake reset_type_3 reset_type_4 p1_pocony.pdmx fpclk
TLE9843QX system control unit - digital modules (scu-dm) data sheet 28 rev. 1.0, 2016-05-06 ? reset_type_4; peripheral reset (without soft) ? baudrate generator: ?f br ; baudrate clock for uart ? port control: ? p0_pocony.pdmx; driver strength control ? p1_pocony.pdmx; driver strength control ?misc: ? modpiselx; mode selection registers for uart (source selection) and timer (trigger or count selection)
TLE9843QX system control unit - digital modules (scu-dm) data sheet 29 rev. 1.0, 2016-05-06 6.3 clock generation unit the clock generation unit (cgu) prov ides a flexible clock generation fo r TLE9843QX. during user program execution the frequency can be programmed for an opti mal ratio between performance and power consumption. therefore the power consumption can be adapted to the actual application state. the cgu in the TLE9843QX consists of one oscillator circuit (osc_h p), a phase-locked loop (pll) module including an internal oscilla tor (osc_pll) and a clock co ntrol unit (ccu). the cgu can convert a low-frequency input/external clock signal to a high-frequency internal clock. the system clock f sys is generated out of the following selectable clocks: ? pll clock output f pll ? direct clock from oscillator osc_hp f osc ? direct output of internal oscillator f intosc ? low precision clock f lp_clk (hw-enabled for startup after reset and during power-down wake-up sequence) the following sections describe t he different parts of the cgu. 6.3.1 low precision clock the clock source lp_clk is a low-pr ecision rc oscillator (lp-osc, see f lp_clk ) that is enabled by hardware as an independent clock source for the TLE9843QX startup after reset and during the power-down wake-up sequence. there is no user configuration possible on f lp_clk . 6.3.2 high precisi on oscillator ci rcuit (osc_hp) the high precision oscillator circuit, designed to work with both an external crystal os cillator or an external stable clock source, consists of an inverting amplif ier with xtal1 as input, and xtal2 as output. figure 11 shows the recommended external circuitries for both operating modes, external crystal mode and external input clock mode. 6.3.2.1 external input clock mode when supplying the clock signal direct ly, not using an external crystal a nd bypassing the oscillator, the input frequency needs to be within the range of 4 mhz to 24 mhz if the pll vco part is used. when using an external clock signal it must be connected to xtal1. xtal2 is left open (unconnected). 6.3.2.2 external crystal mode when using an external crystal, its fr equency can be within the range of 4 mhz to 6 mhz. an external oscillator load circuitry must be used, connected to both pins, xtal1 and xtal2. it consists normally of the two load capacitances c1 and c2, for some crystals a series da mping resistor might be necessary. the exact values and related operating range are dependent on the crystal and have to be determined and optimized together with the crystal vendor using the negative resistance method. as starting point for the evaluation, the following load cap values may be used: table 5 external cap capacitors fundamental mode crystal frequency (approx., mhz) load caps c 1 , c 2 (pf) 433 522 618
TLE9843QX system control unit - digital modules (scu-dm) data sheet 30 rev. 1.0, 2016-05-06 figure 11 TLE9843QX external circuitry for the osc_hp ext_osc osc_hp c 1 4 - 6 mhz c 2 xtal1 xtal2 osc_hp xtal1 xtal2 external clock signal fundamental mode crystal external crystal mode external input clock mode v ddp f osc f osc v ss v ss v ddp v ss = gnd
TLE9843QX system control unit - digital modules (scu-dm) data sheet 31 rev. 1.0, 2016-05-06 6.3.3 clock control unit the clock control unit (ccu) re ceives the clock from the pll f pll , the external input clock f osc , the internal input clock f intosc , or the low-precision input clock f lp_clk . the system frequency is deri ved from one of these clock sources. figure 12 clock inputs to clock control unit the ccu generates all nece ssary clock signals within the microcontroller from the system clock. it consists of: ? clock slow down circuitry ? centralized enable/disable circuit for clock control in normal running mode, the main module frequencies (synchronous unless otherwise stated) are as follows: ? system frequency, f sys = up to 25 mhz ( measurement interface clock mi_clk is derived from this clock) ? cpu clock (cclk, sclk) = up to 25 mhz (divide-down of nvm access clock) ? nvm access clock (nvmaccclk) = up to 25 mhz ? peripheral clock (pclk, pclk2, nvmclk) = up to 25 mhz (equals cpu clock; must be same or higher) some peripherals are clocked by pclk, others clocked by pclk2 and the nvm is clocked by both nvmclk and nvmaccclk. during normal running mode, pclk = pclk2 = nvmclk = cclk. on wake-up from power-down mode, pclk2 is restored similarly like nvmclk, wher eas pclk is restored only after pll is locked. for optimized nvm access (read/write) with reduced wait state(s) and with respec t to system requirements on cpu operational frequency, bit field nvmclkfac is prov ided for setting the frequency factor between the nvm access clock nvmaccclk and the cpu clock cclk. for the slow down mode, the operating frequency is reduc ed using the slow down circuitry with clock divider setting at the bit field clkrel. bit field clkrel is only effective when slow down mode is enabled via sfr bit pmcon0.sd bit. note that the slow down setting of bit field clkrel correspond ingly reduces the nvmaccclk clock. slow down setting does not influen ce the erase and write cycles for the nvm. peripherals uart1, uart2, t2 and t21 and are not in fluenced by clkrel and either not by nvmclkfac, to allow functional lin comm unication in slow down mode. ccu_ block m u x ccu scu_syscon0. sysclksel f sys f lp _clk f intosc f osc f pll
TLE9843QX system control unit - digital modules (scu-dm) data sheet 32 rev. 1.0, 2016-05-06 figure 13 clock generation from f sys ; clkout generation cordic lp-osc watchdog timer clkrel nvm corel toggle latch tlen m u x f sys clkout clock control unit nvmaccclk nvmclkfac nvmclk couts1 f lp _clk mi_clk measurement interface apclk1fac analog subsystem / pba0 / pba1 cclk sclk pclk core peripherals f cclk pclk2 peripherals apclk2fac analog peripherals sfr pclk2 mi_clk tfilt_clk mi_clk tfilt_clk peripherals peripherals pba0clkrel f pll f intosc f osc uart 1/2, timer 2/21, baudgen 1/2 f sys
TLE9843QX system control unit - power modules (scu-pm) data sheet 33 rev. 1.0, 2016-05-06 7 system control unit - power modules (scu-pm) 7.1 description of the powe r modules system control unit the system control unit of the power modul es consists of the following sub-modules: ? clock watchdog unit (cwu): superv ision of all power m odules relevant clocks with nmi signalling. ? interrupt control unit (icu ): all system relevant interr upt flags and status flags. ? power control unit (pcu): takes over control wh en device enters and exits sleep and stop mode. ? external watchdog (wdt1): independent syst em watchdog to monitor system activity 7.2 introduction 7.2.1 block diagram the system control unit of the power modules consis ts of the sub-modules in the figure shown below: figure 14 block diagram of system control unit - power modules io description of scu_pm: cwu (clock watchdog unit) ? check of f sys = system frequency: output of pll ? check of mi_clk = measurement interface clock (analog clock): derived out of f sys by division factors 1/2/3/4 ? check of tfilt_clk = clock used fo r digital filters: derived out of f sys by configurable division factors scu_ pm_block_diagram_ cust.vsd system control unit -power modules pcu amba ahb on signals to analog peripherals; status signals from analog peripherals cwu fsys mi_clk tfilt_clk wdt1 icu i n t e r n a l b u s prewarn_sup_nmi prewarn_clk_int int lp_clk
TLE9843QX system control unit - power modules (scu-pm) data sheet 34 rev. 1.0, 2016-05-06 icu (interrupt control unit) ? prewarn_sup_nmi = generation of prewarn-supply nmi ? prewarn_clk_int = generation of prewarn-clock watchdog nmi ? int = generation of misc interrupts
TLE9843QX arm cortex-m0 core data sheet 35 rev. 1.0, 2016-05-06 8 arm cortex-m0 core 8.1 features the key features of the cortex -m0 implemented are listed below. processor core. a low gate count core, with low latency interrupt processing: ?thumb ? + thumb-2 ? instruction set ? banked stack pointer (sp) only ? handler and thread modes ? thumb and debug states ? interruptible-continued instructions ldm/ stm, push/pop for low interrupt latency ? automatic processor st ate saving and restoration for low latency in terrupt service routine (isr) entry and exit ? arm architecture v6-m style ? armv6 unaligned accesses ? systick (typ. 1ms) nested vectored interrupt controller (nvic) closely integrated with the processor core to achieve low latency interrupt processing: ? external interrupts, configurable from 1 to 24 ? 7 interrupt priority registers for levels from 0 up to 192 in steps of 64 ? dynamic reprioriza tion of interrupts ? priority grouping. this enables selection of pre-empti ng interrupt levels and non pre-empting interrupt levels ? support for tail-chaining and late arrival of interrupts . this enables back-to-back interrupt processing without the overhead of state saving an d restoration between interrupts. ? processor state automatically saved on interrupt entr y, and restored on interrupt exit, with no instruction overhead bus interfaces ? advanced high-performance bus- lite (ahb-lite) interfaces
TLE9843QX arm cortex-m0 core data sheet 36 rev. 1.0, 2016-05-06 8.2 introduction the arm cortex-m0 processor is a leading 32-bit processo r and provides a high-performance and cost-optimized platform for a broad range of applications including microcontrollers, automotive body systems and industrial control systems. like the other co rtex-family processors, the cortex-m0 processor implements the thumb ? -2 instruction set architecture. with the optimized feature set the cortex -m0 delivers 32-bit performance in an application space that is usually associat ed with 8- and 16-bit microcontrollers. 8.2.1 block diagram figure 15 shows the functional blocks of the cortex-m0. figure 15 cortex-m0 block diagram cortex_ m0 _block_diagram .vsd bus matrix debugger interface cortex-m0 processor core nested vectored interrupt controller (nvic) serial-wire debug access port (sw-dp) cortex-m0 processor serial-wire debug interface interrupt and power control ahb-lite interface breakpoint and watchpoint unit
TLE9843QX address space organization data sheet 37 rev. 1.0, 2016-05-06 9 address space organization the embedded cortex-m0 mcu offers the following address space organization: figure 16 original cortex-m0 memory map the TLE9843QX manipulates operands in the following memory spaces: ? 48 kbyte of flash memory in code space ? 24 kb boot rom memory in code space (used for boot code and ip storage) ? 4 kb ram memory in code space and data space (ram ca n be read/written as program memory or external data memory) ? special function registers (sfrs) in peri pheral linear address space, up to 0.5 gbytes the figure below shows the detailed address alignment of TLE9843QX:
TLE9843QX address space organization data sheet 38 rev. 1.0, 2016-05-06 the on-chip memory modules available in the TLE9843QX are: figure 17 TLE9843QX memory map memorymaparm0_4x.vsd boot-rom 24k flash up to 64k *) reserved sram up to 4k *) reserved pba0 pba1 reserved private peripheral bus reserved 0000 .5 fff h 0000 .0000 h 1100.ffff h 1100.0000 h reserved 10ff.ffff h 0000.6000 h 1101.0000 h 17ff.ffff h 1800 .0 fff h 1800.0000 h 1800.1000 h 3fff.ffff h e010.0000 h ffff.ffff h 6000.0000 h dfff.ffff h 4000.0000 h 5fff.ffff h e000.0000 h e00f.ffff h 4800.0000 h 47ff.ffff h *) product variant dependant
TLE9843QX memory control unit data sheet 39 rev. 1.0, 2016-05-06 10 memory control unit 10.1 features ? provides memory access to rom, ram, nvm, config sector through ahb-lite interface ? mbist for ram ? mbist for rom ? nvm configuration with special function registers through ahb-lite interface ? hardware memory protection logic 10.2 introduction 10.2.1 block diagram the memory control unit is divi ded in the following sub-modules: ? nvm memory module (embedded flash memory) ? ram memory module ? bootrom memory module ? memory protection unit (mpu) module
TLE9843QX memory control unit data sheet 40 rev. 1.0, 2016-05-06 figure 18 memory control unit block view functional features for ram ?4 kb ram ? error correction code (ecc) for detect ion of single bit and double bit errors and dynamic correction of single bit errors ? single byte access mcu_block_diagram_overview.vsd bus matrix ram rom s0 memory protection unit s1 s2 nvm code/ data m1 m2 ram code/ data rom code/ data m0 pba0 s3 m3 sx: bus slave mx: bus master nvm
TLE9843QX nvm module (flash memory) data sheet 41 rev. 1.0, 2016-05-06 11 nvm module (flash memory) the flash memory provides an embedded user-programma ble non-volatile memory, allowing fast and reliable storage of user code and data. features ? in-system programming via lin (flash mode) and swd ? error correction code (ecc) for detection of single bit and double bit errors and dynamic correction of single bit errors on data block (double words, 64 bits). ? interrupt and signaling of double bit error by nmi, address of double bit error readable by fw api user routine. ? possibility of checking single bi t error occurrence by rom routines ? program width of 128 byte (page) ? minimum erase width of 128 byte (page) ? integrated hardw are support for eeprom emulation ? 8 byte read access ? physical read access time: typ. 75 ns ? code read access acceleration integrated; read buffer ? page program time: typ. 3 ms ? programming time for 64kb via debug interface: < 1800 ms (typ.) ? page erase (128 bytes) and sector erase (4k bytes) time: typ. 4ms ? 3 separate keys for data area, program area and bsl area ? password protection for three configurable program flash areas, three separate keys for data, program and bsl ? security option to protect read out via debug interface in application run mode. nvm pr otection mode available, which can be enabled/disabled with password ? write/erase access to 100tp (e.g. option bytes) is poss ible via the debug interface note: the user has to ensure that no flash operations whic h change the content of the flash get interrupted at any time. the clock for the nvm is supplied with the system frequency f sys . integrated firmware routines are provided to ease nvm, and other operations including eeprom emulation. the TLE9843QX nvm module provides physical implementation of the memory module as well as needed complementary features and interface towards the core. the module provides proper access to the memory through 2 ahb-lite interfaces: a 8-bit data interface for nvm internal register access and a 32-bit data interface for code/data access both multiplexed on cortex-m0 system bus. the TLE9843QX nvm module consists of the memory cell array and all the control circuits and registers needed to access the array itself. the 64 kbyte data module is mapped in the cortex-m0 code address range 11000000h - 1100ffffh while the dedicated sfrs are mapped in the cortex-m0 system address range . access of nvm module is granted through the amba matrix block that forwards to the memory modules ahb-lite interfaces the requests generated by the mast ers according to the defined priority policy.
TLE9843QX nvm module (flash memory) data sheet 42 rev. 1.0, 2016-05-06 11.1 definitions this section defines the nomenclature and some abbrevia tions. the used flash memory is a non-volatile memory (?nvm?) based on a floating gate one-tr ansistor cell. it is called ?non-volat ile? because the memory content is kept when the memory power supply is shut off. 11.1.1 general definitions logical and physical states erasing the erased state of a cell is 1. forcing an nvm cell to this state is called erasin g. erasing is possible with a granularity of a page (see below). writing the written state of a cell is 0. forc ing an nvm cell to this state is called writing. each bit can be individually written. programming the combination of erasing and writ ing is called ?programming?. programming often means also writing a previously erased page. the wording ?write? or ?writing? are al so used for accessing special function registers and the assembly buffer. the meaning depends therefore on the context. the above listed processes have certain limitations: retention: this is the time during wh ich the data of a flash cell can be read reliably. the retention time is a statistical figure that depends on the operating conditions of the flash arra y (temperature profile) and the accesses to the flash array. with an increasing number of program/ erase cycles (see en durance) the rete ntion is lowered. drain and gate disturbs decrease data retention as well. endurance: as described abov e, the data retention is reduced with an in creasing number of program/erase cycles. a flash cell incurs one cycle whenever its page or sector is erased. this number is called ?endurance?. as said for the retention, it is a statistical figu re that depend on operating conditions a nd the use of the flash cells and on the required quality level. drain disturb: because of using a so called ?one-transistor? flash cell each program access disturbs all pages of the same sector slightly. over long these ?drain disturbs ? make 0 and 1 values indistinguishable and thus provoke read errors. this effect is again interr elated with the retention. a cell that incurred a high number of drain disturbs will have a lower retention. the physical sectors of the flash array are isolat ed from each other. so pages of a different sector do not incur a drain disturb. this effect must be therefore considered when the page erase feature is used or when re-programming an ready programmed pag e (implicitly causing an erase of the page before writing the new data). data portions
TLE9843QX nvm module (flash memory) data sheet 43 rev. 1.0, 2016-05-06 figure 19 logical structure of the nvm core doubleword a doubleword consists of 64 bits. a doubleword represents the data size that is read from or written to the nvm core module within one access cycle. block a block consists of one doubleword and its associated ecc data (64 bit data and 8 bit ecc). a block represents the smallest data portion that can be changed in the asse mbly buffer. since the ecc pr otects 64 bits, when a byte is written to the assembly buffer automatically an nvm inte rnal read of the complete block is triggered, the byte and the ecc are updated and the complete block is written back to the assembly buffer. mapblock a map block consists of a module spec ific number of ecc -protected bits th at hold the necessary information to map a physical page to a logical page. page a page consists of 16 blocks and one map block. spare page sector n-1 sector 1 sector 0 nvm array(n-1)*4 kb page 0 page 1 spare page page 31 page 30 map block data block 0 data block 1 data block 15 data block 14 1 page = 16 user data block + 1 mapping information block byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 1 block = 8 bytes nvm logical structure
TLE9843QX nvm module (flash memory) data sheet 44 rev. 1.0, 2016-05-06 a spare page is an additional page in a sector used in each programming routine to allow tearing-safe programming. sector a sector consists of 32 logical and 33 physical pages.
TLE9843QX interrupt system data sheet 45 rev. 1.0, 2016-05-06 12 interrupt system 12.1 features ? up to 24 interrupt nodes for on-chip peripherals ? up to 8 nmi nodes for critical system events ? maximum flexibility fo r all 24 interrupt nodes 12.2 introduction 12.2.1 overview the TLE9843QX supports 24 interrupt vectors with 4 priori ty levels. 22 of these interrupt vectors are assigned to the on-chip peripherals: gpt12, ssc1, ssc2, ccu6, lo w-side switch, high-side switch and a/d converter are each assigned to one dedicated interrupt vector; while uart1 and timer2 or uart2, external interrupt 2 and timer21 share interrupt vectors. two vectors are dedicated for external interrupt 0 and 1. table 6 interrupt vector table service request node id description gpt1 0 gpt1 interrupt gpt2 1 gpt2 interrupt mu 2 mu interrupt / ad c2, vbg interrupt adc1 3 adc10 bit interrupt ccu0 4 ccu6 node 0 interrupt ccu1 5 ccu6 node 1 interrupt ccu2 6 ccu6 node 2 interrupt ccu3 7 ccu6 node 3 interrupt ssc1 8 ssc1 interrupt (receive, transmit, error) ssc2 9 ssc2 interrupt (receive, transmit, error) uart1 10 uart1 (asc-lin) interrupt (r eceive, transmit), t2, linsync1, lin uart2 11 uart2 interrupt (rec eive, transmit), t21, external interrupt (eint2) exint0 12 external interrupt (eint0), wakeup exint1 13 external in terrupt (eint1) wakeup 14 wakeup interupt (generated by a wakeup event) rfu 15 reserved for future use rfu 16 reserved for future use ls1 17 low side 1 interrupt ls2 18 low side 2 interrupt hs1 19 high side 1 interrupt rfu 20 reserved for future use rfu 21 reserved for future use
TLE9843QX interrupt system data sheet 46 rev. 1.0, 2016-05-06 monx 22 monx interrupt, wakeup port 2.x 23 port 2.x - dpp1 table 7 nmi interrupt table service request node description pll nmi nmi pll loss-of-lock nvm operation complete nmi nmi nvm operation complete overtemperature nmi nmi system overtemperature oscillator watchdog nmi nmi oscillator watchdog and mi_clk watchdog timer overflow nvm map error nmi nmi nvm map error ecc error nmi nmi ram / nvm uncorrectable ecc error supply prewarning nmi nmi supply prewarning table 6 interrupt vector table (cont?d) service request node id description
TLE9843QX watchdog timer (wdt1) data sheet 47 rev. 1.0, 2016-05-06 13 watchdog timer (wdt1) 13.1 features in active mode, the wdt1 acts as a windowed watchdog timer, which provides a high ly reliable and safe way to recover from software or hardware failures. the wdt1 is always enabled in active mode. in sleep mo de, stop mode and debug mode the wdt1 is disabled. functional features ? watchdog timer is operating wit h a from the system clock ( f sys ) independent clock source ( f lp_clk ) ? windowed watchdog timer with programmable timing (1 6, 32, 48, ?, 1008ms period) in active mode ? long open window (200 ms) after power-up, reset, wake-up ? short open window (30 ms) to facilitate fl ash programming ? system safety shutdown to sleep mo de after 5 missed wdt1 services ? watchdog is disabled in debug mode ? watchdog cannot be deactivated in normal mode ? watchdog reset is stored in reset status register
TLE9843QX watchdog timer (wdt1) data sheet 48 rev. 1.0, 2016-05-06 13.2 introduction the behavior of the watchdog timer in active mode is depicted in figure 20 . figure 20 watchdog timer behavior trigger always timeout reset reset reset trigger sow trigger sow trigger timeout or trigger in closed window reset power-up timeout long open window normal ?windowed? operation short open window trigger maximum number of sow triggers exceeded trigger sow
TLE9843QX gpio ports and peripheral i/o data sheet 49 rev. 1.0, 2016-05-06 14 gpio ports and peripheral i/o the TLE9843QX has 18 port pins organized into three paralle l ports: port 0 (p0), port 1 (p1) and port 2 (p2). each port pin has a pair of internal pull-up and pull-down devi ces that can be individually enabled or disabled. p0 and p1 are bidirectional and can be used as general purpose input/output (gpio) or to perform alternate input/output functions for the on-chip peri pherals. when configured as an output, the open drain mode can be selected. on port 2 (p2) analog inputs are shared with general purpose input. 14.1 features ? 10 gpios (p0.x & p1.x), 6 analog inputs (p2.x) and tw o additional analog inputs shared with a xtal feature (p2.4, p2.5). ? strong pull-up at reset-pin and hall-inputs (except p2.x) bidirectional port features (p0, p1) ? configurable pin direction ? configurable pull-up/ pull-down devices ? configurable open drain mode ? configurable drive strength ? transfer of data through digital inputs and outputs (general purpose i/o) ? alternate input/output for on-chip peripherals analog port features (p2) ? configurable pull-up/ pull-down devices ? transfer of data through digital inputs ? alternate inputs for on-chip peripherals 14.2 introduction
TLE9843QX gpio ports and peripheral i/o data sheet 50 rev. 1.0, 2016-05-06 14.2.1 port 0 and port 1 figure 21 shows the block diagram of an TLE9843QX bidirectional port pin. each port pin is equipped with a number of control and data bits, thus ena bling very flexible usage of the pin. figure 21 general structure of bidirectional port od open drain control register data data register altdataout 3 altdataout 2 altsel0 alternate select register 0 altsel1 alternate select register 1 altdatain puden pull-up / pull-down enable register dir direction register pudsel pull-up / pull-down select register pull-up / pull-down control logic altdataout 1 pad out in pull device output driver input driver schmitt trigger px_pocony port output driver control registers tccr temperature compensation control register port_block_diagram.vsd i n t e r n a l b u s 11 10 00 01 analogin
TLE9843QX gpio ports and peripheral i/o data sheet 51 rev. 1.0, 2016-05-06 14.2.2 port 2 figure 22 shows the structure of an input-on ly port pin. each p2 pin can onl y function in input mode. register p2_dir is provided to enable or disable the input driver. wh en the input driver is enabl ed, the actual voltage level present at the port pin is translated into a logic 0 or 1 vi a a schmitt-trigger device and can be read via the register p2_data. each pin can also be programmed to activate an internal weak pull-up or pull-down device. register p2_pudsel selects whether a pull-up or the pull-down de vice is activated while register p2_puden enables or disables the pull device. the analog input (analogin) bypass es the digital circuitry and schmitt-trigger device for direct feed-through to the adc input channel. figure 22 general structure of input port data data register internal bus altdatain puden pull-up/pull-down enable register pudsel pull-up/pull-down select register pull-up/pull-down control logic pad in pull device input driver schmitt trigger analogin port_inputdiagram .vsd
TLE9843QX gpio ports and peripheral i/o data sheet 52 rev. 1.0, 2016-05-06 14.3 TLE9843QX port impl ementation details 14.3.1 port 0 14.3.1.1 port 0 functions port 0 alternate function mapping according table 8 table 8 port 0 input/output functions port pin input/output select connected signal(s) from/to module p0.0 input gpi p0_data.p0 inp1 t12hr_0 ccu6 inp2 t4ina gpt12 inp3 t2_0 timer 2 inp4 swd_clk swd inp5 exint2_3 scu output gpo p0_data.p0 alt1 t3out_0 gpt12 alt2 exf21_0 timer 21 alt3 uart2_rxdo uart2 p0.1 input gpi p0_data.p1 inp1 t13hr_0 ccu6 inp2 uart1_rxd uart1 inp3 t2ex_1 timer 2 inp4 t21_0 timer 21 inp5 exint0_3 scu inp6 t4inc gpt12 inp7 capina gpt12 inp8 ssc12_s_sck ssc1/2 inp9 cc62_0 ccu6 output gpo p0_data.p1 alt1 t6out_0 gpt12 alt2 cc62_0 ccu6 alt3 ssc12_m_sck ssc1/2
TLE9843QX gpio ports and peripheral i/o data sheet 53 rev. 1.0, 2016-05-06 p0.2 input gpi p0_data.p2 inp1 t2euda gpt12 inp2 ctrap_0 ccu6 inp3 ssc12_m_mrst ssc1/2 inp4 t21ex_0 timer 21 inp5 exint1_3 scu output gpo p0_data.p2 alt1 ssc12_s_mrst ssc1/2 alt2 uart1_txd uart1 alt3 exf2_0 timer 2 p0.3 input gpi p0_data.p3 inp1 ssc1_s_sck ssc1 inp2 t4euda gpt12 inp3 capinb gpt12 inp4 exint1_2 scu inp5 t3eudd gpt12 inp6 ccpos0_1 ccu6 output gpo p0_data.p3 alt1 ssc1_m_sck ssc1 alt2 t6ofl gpt12 alt3 t6out_1 gpt12 p0.4 input gpi p0_data.p4 inp1 ssc1_s_mtsr ssc1 inp2 cc60_0 ccu6 inp3 t21_2 timer 21 inp4 exint2_2 scu inp5 t3euda gpt12 inp6 ccpos1_1 ccu6 output gpo p0_data.p4 alt1 ssc1_m_mtsr ssc1 alt2 cc60_0 ccu6 alt3 clkout_0 scu table 8 port 0 input/output functions (cont?d) port pin input/output select connected signal(s) from/to module
TLE9843QX gpio ports and peripheral i/o data sheet 54 rev. 1.0, 2016-05-06 p0.5 input gpi p0_data.p5 inp1 ssc1_m_mrst ssc1 inp2 exint0_0 scu inp3 t21ex_2 timer 21 inp4 t5ina gpt12 inp5 ccpos2_1 ccu6 output gpo p0_data.p5 alt1 ssc1_s_mrst ssc1 alt2 cout60_0 ccu6 alt3 lin_rxd lin table 8 port 0 input/output functions (cont?d) port pin input/output select connected signal(s) from/to module
TLE9843QX gpio ports and peripheral i/o data sheet 55 rev. 1.0, 2016-05-06 14.3.2 port 1 14.3.2.1 port 1 functions port 1alternate function mapping according table 9 table 9 port 1 input / output functions port pin input/output select connected signal(s) from/to module p1.0 input gpi p1_data.p0 inp1 t3inc gpt12 inp2 cc61_0 ccu6 inp3 ssc2_s_sck ssc2 inp4 t4eudb gpt12 output gpo p1_data.p0 alt1 ssc2_m_sck ssc2 alt2 cc61_0 ccu6 alt3 uart2_txd uart2 p1.1 input gpi p1_data.p1 inp1 t6euda gpt12 inp2 t5inb gpt12 inp3 t3eudc gpt12 inp4 ssc2_s_mtsr ssc2 inp5 t21ex_3 timer 21 inp6 uart2_rxd uart2 output gpo p1_data.p1 alt1 ssc2_m_mtsr ssc2 alt2 cout61_0 ccu6 alt3 exf21_1 timer 21 p1.2 input gpi p1_data.p2 inp1 exint0_1 scu inp2 t21_1 timer 21 inp3 t2ina gpt12 inp4 ssc2_m_mrst ssc2 inp5 ccpos2_2 ccu6 output gpo p1_data.p2 alt1 ssc2_s_mrst ssc2 alt2 cout63_0 ccu6 alt3 t3out_1 gpt12
TLE9843QX gpio ports and peripheral i/o data sheet 56 rev. 1.0, 2016-05-06 p1.4 input gpi p1_data.p4 inp1 exint2_1 scu inp2 t21ex_1 timer 21 inp3 t2inb gpt12 inp4 t5euda gpt12 inp5 ssc12_s_mtsr ssc1/2 inp6 ccpos1_2 ccu6 output gpo p1_data.p4 alt1 clkout_1 scu alt2 cout62_0 ccu6 alt3 ssc12_m_mtsr ssc1/2 table 9 port 1 input / output functions (cont?d) port pin input/output select connected signal(s) from/to module
TLE9843QX gpio ports and peripheral i/o data sheet 57 rev. 1.0, 2016-05-06 14.3.3 port 2 14.3.3.1 port 2 functions port 2 alternate function mapping according table 10 table 10 port 2 input functions port pin input/output select connected signal(s) from/to module p2.0 input gpi p2_data.p0 inp1 exint1_1 scu inp2 ccpos0_2 ccu6 inp3 t5eudb gpt12 analog an0 adc p2.1 input gpi p2_data.p1 inp1 ccpos0_0 ccu6 inp2 exint1_0 scu inp3 t12hr_1 ccu6 inp4 cc61_1 ccu6 analog an1 adc p2.2 input gpi p2_data.p2 inp1 t6eudb gpt12 inp2 t2ex_0 timer 2 inp3 t12hr_2 ccu6 analog an2 adc p2.3 input gpi p2_data.p3 inp1 ccpos1_0 ccu6 inp2 exint0_2 scu inp3 ctrap_1 ccu6 inp4 t3ind gpt12 inp5 cc60_1 ccu6 analog an3 adc p2.4 input gpi p2_data.p4 inp1 t2eudb gpt12 inp2 t2_2 timer 2 inp3 t2ex_2 timer 2 inp4 ccpos0_3 ccu6 inp5 ctrap_2 ccu6 in xtal (in) 1) xtal
TLE9843QX gpio ports and peripheral i/o data sheet 58 rev. 1.0, 2016-05-06 p2.5 input / output gpi p2_data.p5 inp1 t3eudb gpt12 inp2 t4eudc gpt12 inp3 t2_1 timer 2 inp4 lin_txd lin inp5 ccpos1_3 ccu6 out xtal (out) 1) xtal p2.6 input gpi p2_data.p6 inp1 t4eudd gpt12 inp2 t2ex_3 timer 2 inp3 ccpos2_3 ccu6 inp4 t13hr_2 ccu6 analog an6 adc p2.7 input gpi p2_data.p7 inp1 ccpos2_0 ccu6 inp2 exint2_0 scu inp3 t13hr_1 ccu6 inp4 cc62_1 ccu6 analog an7 adc 1) configurable by user table 10 port 2 input functions (cont?d) port pin input/output select connected signal(s) from/to module
TLE9843QX general purpose timer units (gpt12) data sheet 59 rev. 1.0, 2016-05-06 15 general purpose timer units (gpt12) 15.1 features 15.1.1 features block gpt1 the following list summarizes the supported features: ? f gpt /4 maximum resolution ? 3 independent timers/counters ? timers/counters can be concatenated ? 4 operating modes: ?timer mode ? gated timer mode ? counter mode ? incremental interface mode ? reload and capture functionality ? shared interrupt: node 0 15.1.2 features block gpt2 the following list summarizes the supported features: ? f gpt /2 maximum resolution ? 2 independent timers/counters ? timers/counters can be concatenated ? 3 operating modes: ?timer mode ? gated timer mode ? counter mode ? extended capture/reload functions via 16-bit capture/reload register caprel ? shared interrupt: node 1 15.2 introduction the general purpose timer unit blocks gpt1 and gpt2 have very flexible multifunctional timer structures which may be used for timing, event counting, pulse width meas urement, pulse generation, frequency multiplication, and other purposes. they incorporate five 16-bit timers that are grouped into the two timer blocks gpt1 and gpt2. each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. each block has alternate input/output functions and spec ific interrupts associated with it. input signals can be selected from several sources by register pisel. the gpt module is clocked with clock f gpt . f gpt is a clock derived from f sys .
TLE9843QX general purpose timer units (gpt12) data sheet 60 rev. 1.0, 2016-05-06 15.2.1 block diagram gpt1 block gpt1 contains three timers/counters: the core timer t3 and the two auxiliary timers t2 and t4. the maximum resolution is f gpt /4. the auxiliary timers of gp t1 may optionally be configur ed as reload or capture registers for the core timer. figure 23 gpt1 block diagram (n = 2 ? 5) t3 mode control 2 n : 1 f gp t t2 mode control t4 mode control aux. timer t4 reload capture core timer t3 t3otl t4in t4eud toggle latch u/d interrupt request (t2irq) interrupt request (t3irq) interrupt request (t4irq) t3out basic clock t3con.bps1 mc _gpt0101_bldiax1.vsd t3in t3eud u/d t2in t2eud aux. timer t2 reload capture u/d
TLE9843QX general purpose timer units (gpt12) data sheet 61 rev. 1.0, 2016-05-06 15.2.2 block diagram gpt2 block gpt2 contains two timers/co unters: the core ti mer t6 and the auxiliary time r t5. the maximum resolution is f gpt /2. an additional capture/reload register (caprel) supports capture and reload operation with extended functionality. figure 24 gpt2 block diagram (n = 1 ? 4) caprel mode control 2 n : 1 f gp t t5 mode control t6 mode control gpt2 timer t6 reload clear gpt2 caprel t6otl t6in t6eud toggle ff u/d interrupt request (t5ir) t6ouf interrupt request (t6ir) t6out basic clock t6con.bps2 mc_gpt0108_bldiax4.vsd capin t3in/ t3eud t5in t5eud clear capture u/d gpt2 timer t5 interrupt request (crir)
TLE9843QX timer2 and timer21 data sheet 62 rev. 1.0, 2016-05-06 16 timer2 and timer21 16.1 features ? 16-bit auto-reload mode ? selectable up or down counting ? one channel 16-bit capture mode ? baud-rate generator for u(s)art 16.2 introduction two functionally identical timers are implemented: timer 2 and 21. the description refers to timer 2 only, but applies to timer 21 as well. the timer modules are general purpose 16-bit timer. timer 2 can function as a timer or counter in each of its modes. as a timer, it counts with an input clock of f sys /12 (if prescaler is disabled). as a counter, timer 2 counts 1-to-0 transitions on pin t2. in the counter mode, the maximum resolution for the count is f sys /24 (if prescaler is disabled). 16.2.1 timer2 and time r21 modes overview table 11 port registers mode description auto-reload up/down count disabled ? count up only ? start counting from 16-bit re load value, overflow at ffff h ? reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin t2ex as well ? programmable reload value in register rc2 ? interrupt is generated with reload events.
TLE9843QX timer2 and timer21 data sheet 63 rev. 1.0, 2016-05-06 auto-reload up/down count enabled ? count up or down, direction determined by level at input pin t2ex ? no interrupt is generated ? count up ? start counting from 16-bit re load value, overflow at ffff h ? reload event triggered by overflow condition ? programmable reload value in register rc2 ? count down ? start counting from ffff h , underflow at value defined in register rc2 ? reload event triggered by underflow condition ? reload value fixed at ffff h channel capture ? count up only ? start counting from 0000 h , overflow at ffff h ? reload event triggered by overflow condition ? reload value fixed at 0000 h ? capture event triggered by falling/rising edg e at pin t2ex ? captured timer value stored in register rc2 ? interrupt is generate with reload or capture event table 11 port registers (cont?d) mode description
TLE9843QX capture/compare unit 6 (ccu6) data sheet 64 rev. 1.0, 2016-05-06 17 capture/compare unit 6 (ccu6) 17.1 feature set overview this section gives an overview over the different building blocks and their main features. timer 12 block features ? three capture/compare channels, each channel can be used either as capture or as compare channel ? generation of a three-phase pwm supported (six outp uts, individual signals for high side and low-side switches) ? 16-bit resolution, maximum count frequency = peripheral clock ? dead-time control for each channel to av oid short-circuits in the power stage ? concurrent update of t12 registers ? center-aligned and edge-aligned pwm can be generated ? single-shot mode supported ? start can be controlled by external events ? capability of counti ng external events ? multiple interrupt request sources ? hysteresis-like control mode timer 13 block features ? one independent compare channel with one output ? 16-bit resolution, maximum count frequency = peripheral clock ? concurrent update of t13 registers ? can be synchronized to t12 ? interrupt generation at period-match and compare-match ? single-shot mode supported ? start can be controlled by external events ? capability of counti ng external events additional specific functions ? block commutation for brushl ess dc-drives implemented ? position detection via hall-sensor pattern ? noise filter supported for position input signals ? automatic rotational speed measurement an d commutation control for block commutation ? integrated error handling ? fast emergency stop without cpu load via external signal (ctrap ) ? control modes for multi-channel ac-drives ? output levels can be selected and adapted to the power stage 17.2 introduction the ccu6 unit is made up of a timer t12 block with th ree capture/compare channels and a timer t13 block with one compare channel. the t12 channels can independently generate pwm signals or accept capture triggers, or they can jointly generate control signal pa tterns to drive ac-motors or inverters. a rich set of status bits, synchronize d updating of parameter values via shad ow registers, and flexible generation of interrupt request signals provide means for efficient software-control. note: the capture/compare module itself is named ccu6 (capture/compare unit 6). a capture/compare channel inside this module is named cc6x.
TLE9843QX capture/compare unit 6 (ccu6) data sheet 65 rev. 1.0, 2016-05-06 17.2.1 block diagram the timer t12 can work in capture and/or compare mode for its three channels. the modes can also be combined (e.g. a channel works in compare mode, whereas another channel works in capture mode). the timer t13 can work in compare mode only. the multi-channel control unit generates output patterns which can be modulated by t12 and/or t13. the modulation sources can be sele cted and combined for the signal modulation. figure 25 ccu6 block diagram ccu6 module kernel input / output control port control compare compare 22 compare output select 3 hall input output select 1 trap input 3 capture t13 cc63 start 2 1 multi- channel control trap control dead- time control cc60 cc61 compare 1 1 1 t12 cc62 cout60 cout63 t13hr t12hr ccpos0 ccpos1 ccpos2 ctrap clock control interrupt control f cc 6 sr[3:0] cc61 cout61 cc62 cout62 cc60 debug suspend t13susp t12susp p0. x p1.x p2.x compare ccu6_bd.vsd
TLE9843QX uart1/uart2 data sheet 66 rev. 1.0, 2016-05-06 18 uart1/uart2 18.1 features ? full-duplex asynchronous modes ? 8-bit or 9-bit data frames, lsb first ? fixed or variable baud rate ? receive buffered (1 byte) ? multiprocessor communication ? interrupt generation on the completion of a data transmission or reception ? baud-rate generator with fractional divider for generating a wide range of baud rates, e.g. 9.6kbaud, 19.2kbaud, 115.2kbaud, 125kbaud, 250kbaud, 500kbaud ? hardware logic for break and sync byte detection ? for uart1: lin support: connected to time r channel for synchronization to lin baud rate in all modes, transmission is initiated by any instructio n that uses sbuf as a desti nation register. reception is initiated in the modes by the incoming start bit if ren = 1. the serial interface also provides interrupt requests when transmission or reception of the frames has been completed. the corresponding interrupt request flags are ti or ri, respective ly. if the serial interrupt is not used (i.e., serial interrupt no t enabled), ti and ri c an also be used for pollin g the serial interface. 18.2 introduction the uart1/uart2 provide a full-duplex asynchronous re ceiver/transmitter, i.e., it can transmit and receive simultaneously. they are also receive-buffered, i.e., th ey can commence reception of a second byte before a previously received byte has been read from the receive register. however, if the first byte still has not been read by the time reception of the second byte is complete , the previous byte will be lost . the serial port receive and transmit registers are both accessed at special function register (sfr) sbuf. writin g to sbuf loads the transmit register, and reading sbuf accesses a ph ysically separate receive register.
TLE9843QX uart1/uart2 data sheet 67 rev. 1.0, 2016-05-06 18.2.1 block diagram figure 26 uart block diagram 18.3 uart modes the uart1/uart2 can be used in four different modes. in mo de 0, it operates as an 8-bit shift register. in mode 1, it operates as an 8-bit serial port. in modes 2 and 3, it operates as a 9-bit serial port. the only difference between mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. the variable baud rate is set by the underflow rate on the dedicated baud-rate generator. the different modes are selected by setting bits sm0 and sm1 to their corresponding values, as shown in table 12 . mode 1 example: 8 data bits, 1 start bit, 1 stop bit, no parity selection, 16 times oversampled (majority decision of bits 6, 7, 8), receive & transmit regi ster double buffered, tx/rx irq(s). table 12 uart modes sm0 sm1 operating mode baud rate 0 0 mode 0: 8-bit shift register f sys /2 0 1 mode 1: 8-bit shift uart variable 1 0 mode 2: 9-bit shift uart f sys /64 or f sys /32 1 1 mode 3: 9-bit shift uart variable scu_dm uart disreq from scu _dm uart module ri ti clock control address decoder f uart2 scu_d m interrupt control uart ahb interface rxd txd port control gpios f br baud rate generator urios txd rxd_1 scu_dm rxdo _2 p0 .x p1 .x p2 .x rxd_0
TLE9843QX lin transceiver data sheet 68 rev. 1.0, 2016-05-06 19 lin transceiver 19.1 features general functional features ? compliant to lin2.2 standard, backward compatible to lin1.3 , lin2.0 and lin 2.1 ? compliant to sae j2602 (slew rate, receiver hysteresis) special features ? measurement of lin master baudrate via timer 2 ? lin can be used as input/output with sfr bits. ? txd timeout feature (optional, on by default) ? overcurrent limitation and overtemperature protection ? lin module fully resettable via global enable bit operation modes features ? lin sleep mode (lslm) ? lin receive-only mode (lrom) ? lin normal mode (lnm) ? high voltage input / output mode (lhvio) slope modes features ? normal slope mode (20 kbit/s) ? low slope mode (10.4 kbit/s) ? fast slope mode (62.5 kbit/s) ? flash mode (115 kbit/s, 250 kbit/s) wake-up features ? lin bus wake-up. the wake -up happens on the falling edg e of the lin signal, to allow wake-up and decoding of the same frame. it is possible to enter the sleep mode also with lin dominant (e.g. caused by lin shorted to gnd). 19.2 introduction the lin module is a transceiver for the local interc onnect network (lin) compliant to the lin2.2 standard, backward compatible to lin1.3, lin2.0 and lin2.1. it oper ates as a bus driver between the protocol controller and the physical network. the lin bus is a si ngle wire, bi-directional bus typically used for in-vehicle networks, using baud rates between 2.4 kbaud and 20 kbaud. additionally baud rates up to 62.5 kbaud are implemented. the lin module offers several different operation mode s, including a lin sleep mode and the lin normal mode. the integrated slope control allows to use several data transmission rates with optimized emc performance. for data transfer at the end of line, a flash mode up to 11 5 kbaud is implemented. this flash mode can be used for data transfer under special conditions for up to 250 kbit/s (in production environment, point-to-point communication with reduced wire length and limited supply voltage).
TLE9843QX lin transceiver data sheet 69 rev. 1.0, 2016-05-06 19.2.1 block diagram figure 27 lin transceiver block diagram driver + curr. limit. + tsd lin transceiver sleep comparator gnd_lin rxd_1 to uart receiver vs txd_1 from uart lin_wake 30 k lin_ctrl _sts lin-fsm lin gnd_lin lin_block_diagram_customer.vsd status ctrl status ctrl filter filter transmitter pmu_lin_wake_en.lin_en
TLE9843QX high-speed synchronous serial interface ssc1/ssc2 data sheet 70 rev. 1.0, 2016-05-06 20 high-speed synchronous serial interface ssc1/ssc2 20.1 features ? master and slave mode operation ? full-duplex or half-duplex operation ? transmit and receive double buffered ? flexible data format ? programmable number of data bits: 2 to 16 bits ? programmable shift direction: least significant bi t (lsb) or most signific ant bit (msb) shift first ? programmable clock polarity: idle low or high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock ? variable baud rate, e.g. 250kbaud - 8mbaud ? compatible with serial peripheral interface (spi) ? interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baud rate, transmit error) ? on a transfer complete condition ? port direction selection, see chapter 14 20.2 introduction the high-speed synchronous serial interface (ssc) suppor ts both full-duplex and half-duplex serial synchronous communication. the serial clock signal can be generated by the ssc internally (master mode), using its own 16- bit baud-rate generator, or can be received from an external master (slave mode). data width, shift direction, clock polarity, and phase are programmable. this allows comm unication with spi-compatible devices or devices using other synchronous serial interfaces. data is transmitted or received on lines txd and rxd, which are normally connected to the pins mtsr (mastertransmit/slave receive) and mr st (master receive/slave transmit). the clock signal is output via line ms_clk (master serial shift clock) or input via line ss_cl k (slave serial shift cloc k). both lines are normally connected to the pin sclk. transmission an d reception of data are double-buffered.
TLE9843QX high-speed synchronous serial interface ssc1/ssc2 data sheet 71 rev. 1.0, 2016-05-06 20.2.1 block diagram figure 28 shows all functional relevant interf aces associated with the ssc kernel. figure 28 ssc interface diagram ssc module (kernel) eir tir clock control address decoder rir slave f hw_clk sclk sclka sclkb master scu_dm interrupt control module product interface ahb interface p0.x p1.x p2.x port control ssc_interface_overview.vsd master mrsta mrstb mtsr slave mtsra mtsrb mrst
TLE9843QX measurement unit data sheet 72 rev. 1.0, 2016-05-06 21 measurement unit 21.1 features ? 1 x 10 bit adc with 13 inputs including attenuator allowing measurement of high voltage input signals ? supply voltage attenuators with attenuation of vbat_sense, vs, monx, p2.x . ? 1 x 8 bit adc with 7 inputs including attenuator allowing measurement of high voltage input signals ? supply voltage attenuators with attenuation of vs, vddext, vddp , vbg, vddc, tsense_ls, tsense_central . ? vbg monitoring of 8 bit adc to supp ort functional safety requirements. ? temperature sensor for monitoring the chip temperature and low side module temperature. ? supplement block with reference vo ltage generation, bias current generation, voltage buffer for nvm reference voltage, voltage buffer for analog module reference voltage and test interface. 21.2 introduction the measurement unit is a functional unit that comprises the following associated sub-modules: 21.2.1 block diagram the structure of the measurement functions module is shown in the following figure. table 13 measurement functions and associated modules module name modules functions central functions unit bandgap reference circuit + current reference circuit the bandgap-reference sub-module provides two reference voltages 1. an accurate reference voltage for the 10-bit and 8-bit adcs. a local dedicated bandgap circuit is implemented to avoid deterioration of the reference voltage arising e.g. from crosstalk or ground voltage shift. 2. the reference voltage for the nvm module 10 bit adc (adc1) 10-bit adc module with 13 multiplexed analog inputs vbat_sense, vs and monx measurement. six (5v) analog inputs from port 2.x 8 bit adc (adc2) 8-bit adc module with 7 multiplexed inputs vs/vddext/vddp/vbg/vddc/tsense_ls and tsense_central measurement. temperature sensor temperature sensor readout amplifier with two multiplexed ? vbe- sensing elements generates outputs voltage which is a linear function of the local chip (tj) temperature. measurement core module digital signal processing and adc control unit 1. generates the control signal for the 8-bit adc 2 and the synchronous clock for the switched capacitor circuits (temperature sensor) 2. performs digital signal processing functions and provides status outputs for interrupt generation.
TLE9843QX measurement unit data sheet 73 rev. 1.0, 2016-05-06 figure 29 TLE9843QX measurement unit-overview measurement -unit 8 bit adc + dpp 10 bit adc + dpp mux ch5 ch4 ch3 ch2 ch6 a d vs mux ch2 ch1 ch0 vref a d dpp1 / 10 / 8 dpp2 v bg sfr sfr adc 1 adc 2 pmu bandgap temperature sensor ls x 0.75 vddp vddc x 0.203 ch5 ch4 ch3 ch8 ch7 ch6 ch11 ch10 ch9 x 0.047 x 0.039 x 0.039 x 0.039 x 0.039 x 0.219 x 0.219 x 0.219 x 0.219 ch1 ch0 x 0.039 ch7 temperature sensor central att att x 0.047 x 1 x 1 mon1 mon3 mon4 p2.0 mon2 vbat_sense p2.1 p2.2 p2.3 p2.6 p2.7 x 0.219 rfu vddext x 0.203 rfu ch8 ch12 n.u. x 0.219 vddc x 0.75 x 0.039
TLE9843QX measurement core mo dule (incl. adc2) data sheet 74 rev. 1.0, 2016-05-06 22 measurement core module (incl. adc2) 22.1 features ? 7 individually programmable channels split into two groups of user configurable and non user configurable ? individually programmable channel prioritization scheme for measurement unit ? two independent filter stages with programmable low- pass and time filter characteristics for each channel ? two channel configurations: ? programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis ? two individually programmable trigger th resholds with limit hysteresis settings ? individually programmable interrupts and status for all channel thresholds ? operation down to reset threshold of entire system 22.2 introduction the basic function of this block is the digital postproc essing of several analog digitized measurement signals by means of filtering level comparison and interrupt gene ration. the measurement postprocessing block is built of seven identical channel units attached to the outputs of the 7-channel 8-bit adc (adc2). it processes seven channels, where the channel sequence and prio ritization is programmable within a wide range. 22.2.1 block diagram figure 30 module block diagram digital signal processing 1st order iir mux rfu vddext vddp vddc temperature sensor ls vbg ch6 ch5 ch4 ch3 ch2 ch1 vref calibration unit: y= a + (1+b)*x + - + - th_up_chx th_low_chx / channel controller (sequencer) mux_sel<2:0> a d up_x_sts low_x_sts 3 / 8 + / - + / - / 10 / 8 / 1 / 1 adc2 sos ? eoc adc2 - sfr adc2_out_chx temperature sensor central ch7 vs ch0 / 10 rfu ch8
TLE9843QX 10-bit analog digital converter (adc1) data sheet 75 rev. 1.0, 2016-05-06 23 10-bit analog digital converter (adc1) 23.1 features the basic function of this block is the digital postproc essing of several analog digitized measurement signals by means of filtering, level comparison and interrupt generation. the measurement postprocessing block is built of twelve identical channel units attached to the outputs of the 13-channel 10- bit adc. it processes twelve channels, where the channel sequence and prioritization is programmable within a wide range. functional features ? 10 bit sar adc with conversion time of 17 clock cycles ? programmable clock divider for sequencer and adc ? 12 individually programmable channels (ch0..ch11): ? 6 hv channels: vs, vbat_sense, mon1...mon4 ? 6 lv channels: p2.1, p2 .2, p2.3, p2.6, p2.7, p2.0 ? all channels are fully calibrated and user configurable ? individually programmable channel prioritizati on scheme for digital postprocessing (dpp) ? two independent filter stages with programmable low- pass and time filter characteristics for each channel ? two channel configurations: ? programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis ? two individually programmable trigger th resholds with limit hysteresis settings ? individually programmable upper threshold and lower th reshold interrupts and status for all channel thresholds ? adc reference completely integrated note: in case the monx should be evaluated by the adc1 , it is recommended to add 6.8nf capacitors close to the monx pin of the device, in order to build an exter nal rc filter to limit the bandwidth of the input signal.
TLE9843QX 10-bit analog digital converter (adc1) data sheet 76 rev. 1.0, 2016-05-06 23.2 introduction 23.2.1 block diagram figure 31 module block diagram adc1 - digital post-processing 1st order iir mux vs p2.2 vbat_sense p2.7 p2.1 ch10 ch9 ch8 ch7 ch6 ch2 ch1 ch0 ch11 vref calibration unit: y= a + (1+b)*x + - + - th_up _chx th_low_chx / channel controller (sequencer) mux_sel<3:0> a d up _x_sts low_x_sts 4 / 13*10 + / - + / - / 11*12 / 12*10 adc1 / 1 / 1 10 bit adc adc1_ctrlx sos ? eoc adc - sfr adc_out_chx p2.3 p2.6 adc1 adc1 adc1 mon1 mon2 mon3 mon4 ch3 ch4 ch5 / 12*12 adc_out_chx / 13*12 p2.0
TLE9843QX high-voltage monitor input data sheet 77 rev. 1.0, 2016-05-06 24 high-voltage monitor input 24.1 features features ? 4 high-voltage inputs with vs/2 threshold voltage ? wake capability for system st op mode and system sleep mode ? edge sensitive wake-up feature configurable for transiti ons from low to high, high to low or both directions ? mon inputs can also be evaluated with adc in active mode, using adjustable threshold values (see also chapter 23 ). ? selectable pull-up and pull-down current sources available 24.2 introduction this module is dedicated to monitor external voltage leve ls above or below a specified threshold. each monx pin can further be used to detect a wake-up event by detecting a level change by crossing the selected threshold. this applies to any power mode. further more each monx pin can be sampled by the adc as analog input. 24.2.1 block diagram figure 32 monitoring i nput block diagram monx_input _circuit_ext .vsd sfr logic filter mon + - mon_int mon vs
TLE9843QX high-side switch data sheet 78 rev. 1.0, 2016-05-06 25 high-side switch 25.1 features the high-side switch is optimized for driving resistive loads. only small line inductance are allowed. typical applications are single or mu ltiple leds of a dashboard, switch illuminat ion or other loads that require a high-side switch. a cyclic switch activation during sleep mode or stop mode of the system is also available. functional features ? multi-purpose high-side switch for resistive load connections (only small lin e inductances are allowed) ? overcurrent limitation ? overcurrent detection with thresholds: 25 ma, 50 ma, 100 ma, 150 ma and automatic shutdown ? overtemperature detection and automatic shutdown ? open load detection in on mode with open load current of max. 1.5 ma. ? interrupt signallin g of overcurrent, overtemper ature and open load condition ? cyclic switch activation in sleep mo de and stop mode with cyclic sense support and r educed driver capability: max. 40 ma ? pwm capability up to 25 khz ? internal connection to system-pwm generator (ccu6) ? slew rate control for low emi characteristic applications hints ? the voltage at hsx must not exceed the supply voltage by more than 0.3v to prevent a reverse current from hsx to vs.
TLE9843QX high-side switch data sheet 79 rev. 1.0, 2016-05-06 25.2 introduction 25.2.1 block diagram figure 33 high-side module block diagram (incl. subblocks) 25.2.2 general the high-side switch can generally be controlled in three different ways: ? in normal mode the output stage is fully controllable through the sfr registers hsx_ctrl . protection functions as overcurrent, overtemperatur e and open load detection are available. ? the pwm mode can also be enabled by a hsx_ctrl - sfr bit. the pwm configuration has to be done in the corresponding pwm module. all prot ection functions are also availabl e in this mode. the maximum pwm frequency must not exceed 25 khz (disabled slew rate control only). ? the high-side switch provides also the possibility of cyclic switch acti vation in all low power modes (sleep mode and stop mode). in this configuration it has limited functionality with limited cu rrent capability. diagnostic functions are not available in this mode. high side driver oc-detection ol-detection cyclic- driver sfr 25 ma 50 ma 100 ma 150 ma 1,5 ma on octh_sel olth vs hs
TLE9843QX low-side switch data sheet 80 rev. 1.0, 2016-05-06 26 low-side switch 26.1 features the general purpose low-side switch is optimized to co ntrol an on-board relay. th e low-side switch provides embedded protection functions including overcurrent a nd overtemperature detection. the module is designed for on-board connections. measures for standard esd (hbm) and emc robustness are implemented. functional features ? multi purpose low-side switch optimized for driving relays: ? simple relay driver ? pwm relay driver ? integrated clamping for usag e as a simple relay driver ? overcurrent detection and automatic shutdown ? overtemperature detection and automatic shutdown ? interrupt signalling of overcurr ent and overtemperature condition ? open load detection wi th interrup t signalling ? pwm capability up to 25 khz (for inductive loads with external cl amping circuitry only!) ? selectable pwm source: dedicated ccu6 channels ? current drive capabilit y up to min. 270 ma applications hints ? it is not recommended to use the switch in pwm mode without external free wheeling diode.
TLE9843QX low-side switch data sheet 81 rev. 1.0, 2016-05-06 figure 34 module block diagram 26.2 functional description the low-side switches can generally be controlled in two different ways: ? in normal mode the output stage is fully controllable through the sfr registers lsx_ctrl . protection functions as overcurrent and overtemperature are available. ? the pwm mode can also be enabled by a lsx_ctrl - sfr bit. the pwm configuration has to be done in the corresponding pwm module (ccu6). all protection functi ons are also available in this mode. the maximum pwm frequency must not exceed 25 khz (fast slew rate only). low side driver oc-detection clamp xsfr 270 ma on ls lsgnd
TLE9843QX application information data sheet 82 rev. 1.0, 2016-05-06 27 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. 27.1 relay window lift application diagram figure 35 simplified application diagram example note: this is a very simplified example of an application ci rcuit and bill of material. the function must be verified in the actual application. applicationdiagram_arkas.vsd double hall sensor e.g. tle 4966 v bat lin gnd vbat_sense vs gnd vddc vddp lin mon 1 hs 1 m ls 1 ls 2 cc60 vddext pwm mon 2 mon 3 mon 4 speed direction r vbat_sense c vddext c 2vs c 1vs c vbat_sense1 cc61 hs 2* c lin m+ m- r monx c monx r monx c monx c monx r monx c monx r monx c 1hs c 2hs r 2hs c 1hs c 2hs r 1hs c vddp c vddc c vbat_sense2 * only available in product variants with hs 2
TLE9843QX application information data sheet 83 rev. 1.0, 2016-05-06 27.2 connection of n.c. / n.u. pins the device contains several n.c. (not connected, no bond wire) and n.u. (not used, but bonded) pins. 27.3 connection of unused pins table 16 shows recommendations how to connect pins, in case they are not needed by the application. table 14 external component (bom) symbol function component c 1vs capacitor 1 at vs pin 22 f 1) 1) to be dimensioned according to application requirements c 2vs capacitor 2 at vs pin 100 nf 2)3) 2) to reduce the effect of fast voltage transients of vs, these capacitors should be placed close to the device pin 3) ceramic capacitor c vddext capacitor at vddext pin 330 nf 2) c vddc capacitor at vddc pin 100 nf 2)3) + 330 nf 2) c vddp capacitor at vddp pin 470 nf 2)3) + 470 nf 2) r monx resistor at monx pin 3.9 k ? c monx capacitor at monx connector 6.8 nf 4) 4) for esd gun r vbat_sense resistor at vbat_sense pin 3.9 k ? c vbat_sense1 capacitor 1at vbat_sense pin 10 nf 2) c vbat_sense2 capacitor 2 at vbat_sen se connector 6.8 nf 4) c lin capacitor at lin pin 220 pf r 1hs resistor at hs pin for led e.g. 2.7k ? r 2hs resistor at hs pin 160 ? 5) 5) optional, for short to battery protection, calculated for 24v (jump start) c 1hs capacitor at hs pin 6.8nf 2) c 2hs capacitor at hs connector 33nf 4) table 15 recommendation for c onnecting n.c. / n.u. pins type pin number recommendation 1 recommendation 2 comment n.c. 27, 28, 29, 38, 40, 41 gnd n.c. 10, 46 open gnd neighboring high-voltage pins n.u. 4 vs open n.u. 9 gnd
TLE9843QX application information data sheet 84 rev. 1.0, 2016-05-06 27.4 connection of p0.2 for swd debug mode to enter the swd debug mode, p0.2 needs to be 0 at the rising edge of the reset signal. p0.2 has an internal pulldown, so it just needs to be ens ured that there is no external 1 at p0.2 when the debug mode is entered. 27.5 connection of tms for the debug mode, the tms pin needs to be 1 at the risi ng edge of the reset signal. this is controlled by the debugger. the tms pin has an internal pd. to avoid the device entering the debug mode unintendedly in the final application, adding an external pull-down additionally is recommended. 27.6 esd immunity according to iec61000-4-2 note: tests for esd robustness according to iec61000-4-2 ?gun test? (150pf, 330 ? ) were performed. the results and test condition are available in a test report . the achieved values for the test are listed in table 17 below. table 16 recommendation for connecting unused pins type pin number recommendation 1 (if unused) recommendation 2 (if unused) lin 1 open hs1 3 vs open mon 5, 6, 7, 8 gnd open + configure internal pu/pd ls1, ls2 11, 12 gndls open gpio 14, 15, 16, 17, 20, 22, 23, 24, 25, 26, 33, 34, 35, 36, 37, 39 gnd external pu/pd or open + configure internal pu/pd tms 18 gnd reset 21 open p2/xtal out 31 open p2/xtal in 32 gnd vddext 45 open vbat_sense 48 vs table 17 esd ?gun test? performed test result unit remarks esd at pin lin, versus gnd 6kv 1) positive pulse esd at pin lin, versus gnd -6 kv 1) negative pulse
TLE9843QX application information data sheet 85 rev. 1.0, 2016-05-06 esd at pin vs, vbat_sense, monx, hs, versus gnd 6kv 1) positive pulse esd at pin vs, vbat_sense, monx, hs, versus gnd -6 kv 1) negative pulse 1) esd susceptibility ?esd gun?, tested by external test house (ibee z wickau, emc test report nr . 11-01-16), according to "lin conformance test specification pa ckage for lin 2.1, october 10th, 2008" and "hardware requirements for lin, can and flexray interfaces in automotive application ? aud i, bmw, daimler, porsche, volkswagen ? revision 1.3 / 2012" table 17 esd ?gun test? (cont?d) performed test result unit remarks
TLE9843QX electrical characteristics data sheet 86 rev. 1.0, 2016-05-06 28 electrical characteristics this chapter includes all rele vant electrical characterist ics of the product TLE9843QX. 28.1 general characteristics 28.1.1 absolute maximum ratings table 18 absolute maximum ratings 1) t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. voltages supply pins vs voltage v s,max -0.3 ? 40 v load dump p_1.1.1 vddp voltage v ddp,max -0.3 ? 5.5 v ? p_1.1.2 vddext voltage v ddext,max -0.3 ? v s +0.3 v ? p_1.1.3 vddc voltage v ddc,max -0.3 ? 1.6 v ? p_1.1.4 voltages high voltage pins voltage at vbat_sense pin v bat_sense, max -28 ? 40 v 2) ? p_1.1.5 voltage at hs pin v hs,max -0.3 ? v s +0.3 v ? p_1.1.6 voltage at lin pin v lin,max -28 ? 40 v ? p_1.1.7 voltage at mon_x pins v mon,max -28 ? 40 v 2) p_1.1.8 voltage at ls pin v ls,max -0.3 ? 40 v internal clamping structure > 40v p_1.1.9 voltages gpios voltage on port pin p0.x, p1.x, p2.x, tms and reset v io,max -0.3 ? v ddp +0.3 v v in < v ddpmax 3) p_1.1.10 currents injection current in sleep mode on p0.x, p1.x, p2.x, tms and reset i xx ? ? 5 ma maximum allowed injection current on single pin or sum of pins in sleep mode and unpowered device p_1.1.11 injection current on hs i xlo ? ? 150 ma current flowing into hs pin (back supply in case of short to bat- tery) p_1.1.12
TLE9843QX electrical characteristics data sheet 87 rev. 1.0, 2016-05-06 notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. 28.1.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. output current on ls i ls -300 ? ? ma current flowing out of ls pin, e.g. reverse polarity event (defined in lv124) or iso pulse event (defined in iso 7637-2) p_1.1.13 temperatures junction temperature t j -40 ? 150 c ? p_1.1.14 storage temperature t stg -55 ? 150 c ? p_1.1.15 esd susceptibility esd susceptibility hbm all pins v esd1 -2 ? 2 kv jedec hbm 4) p_1.1.16 esd susceptibility hbm pins lin vs. lingnd v esd3 -6 ? 6 kv jedec hbm 4) p_1.1.17 esd susceptibility cdm v esd_cdm ?500 ? 500 v charged device model, acc. jedec jesd22-c101 p_1.1.18 esd susceptibility cdm pins 1, 12, 13, 24, 25, 36, 37, 48 (corner pins) v esd_cdm ?750 ? 750 v charged device model, acc. jedec jesd22-c101 p_1.1.19 1) not subject to production test, specified by design. 2) for -28v, external 3.9k ? resistor is required to limit output current. 3) one of these limits must be kept. keeping v 4) esd susceptibility, ?jedec hbm? acco rding to ansi/esda/jedec js001 (1.5k ? , 100pf). table 18 absolute maximum ratings 1) (cont?d) t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 88 rev. 1.0, 2016-05-06 28.1.3 current consumption table 19 functional range t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. supply voltage in active mode v s_am 5.5 ? 28 v ? p_1.2.1 extended supply voltage in active mode - range 1 v s_am_exte nd_1 28 ? 40 v functional with parameter deviation 1) 1) this operation voltage range is onl y allowed for a short duration: t max 400 ms. p_1.2.12 extended supply voltage in active mode with reduced functionality (microcontroller / flash with full operation) - range 2 v s_am_exte nd_2 3.0 ? 5.5 v functional with parameter deviation 2) 2) hall-supply, adc, spi, uart, nvm, ram, cpu fully functional and in spec down to 3v vs. actuators (hs, ls) in vs range from 3v < vs < 5.5v functional but some parameters can be out of spec p_1.2.2 specified supply voltage for lin transceiver - active mode v s_am_lin 5.5 ? 18 v parameter specification p_1.2.3 extended supply voltage for lin transceiver - active mode v s_am_lin_ extend 4.8 ? 28 v functional with parameter deviation p_1.2.4 extended supply voltage for lin & monitoring input (mon) - stop & sleep mode v s_ssm_lin _mon_extend 3.6 ? 5.5 v wakeup functionality ensured p_1.2.13 min. supply voltage in stop mode v s_stopmin 3.0 ? ? v p_1.2.5 min. supply voltage in sleep mode v s_sleepmin 3.0 ? ? v p_1.2.6 supply voltage transients slew rate d v s /d t -5?5v/s 3) 3) not subject to production test, specified by design. p_1.2.7 output current on any gpio i oh , i ol -10 ? 10 ma 3) p_1.2.8 output sum current for all gpio pins i gpio,sum -50 ? 50 ma 3) p_1.2.9 operating frequency f sys 4) 4) function not specified when limits are exceeded. 5?25mhz 3) p_1.2.10 junction temperature t j -40 ? 150 c ? p_1.2.11
TLE9843QX electrical characteristics data sheet 89 rev. 1.0, 2016-05-06 table 20 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. current consumption @vs pin current consumption in active mode i vs_freduced ? ? 15 ma fsys = 10 mhz v s = 13.5v all digital modules enabled and functional, adcs converting in sequencer mode, pll running, no loads on gpios, vddext off, lin in recessive state (no communication), hsx & lsx enabled but off 1) p_1.3.1 current consumption in active mode i vs ? 14 18 ma fsys = 25 mhz v s = 13.5v all digital modules enabled and functional, adcs converting in sequencer mode, pll running, no loads on gpios, vddext off, lin in recessive state (no communication), hsx & lsx enabled but off p_1.3.22 current consumption in sleep mode i sleep ? ? 15 a system in sleep mode, microcontroller not powered, wake capable via lin and mon; gpios open (no loads) or connected to gnd: t j = -40c to 25c; v s = 13.5v p_1.3.2 current consumption in sleep mode (extended temperature range) i sleep(t_exte nd) ? ? 25 a system in sleep mode, microcontroller not powered, wake capable via lin and mon; gpios open (no loads) or connected to gnd: t j = 25c to 85c; v s = 13.5v p_1.3.3 current consumption in sleep mode (extended voltage and temperature range) i sleep(v_t_e xtend) ? ? 30 a system in sleep mode, microcontroller not powered, wake capable via lin and mon; gpios open (no loads) or connected to gnd: t j = -40c to 85c; v s = 5.5v to 18v p_1.3.4
TLE9843QX electrical characteristics data sheet 90 rev. 1.0, 2016-05-06 28.1.4 thermal resistance current consumption in sleep mode (extended voltage and temperature range 2) i sleep(v_t_e xtend2) ? ? 40 a system in sleep mode, microcontroller not powered, wake capable via lin and mon; gpios open (no loads) or connected to gnd: t j = -40c to 85c; v s = 3v to 28v p_1.3.7 current consumption in sleep mode with cyclic wake i cyclic ?? 15 a t j = -40c to 25c; v s = 13.5v during sleep period p_1.3.5 current consumption in sleep mode with cyclic wake (extended temperature range) i cyclic(t_exte nd) ?? 30 a t j = 25c to 85c; v s = 13.5v; during sleep period p_1.3.6 current consumption in stop mode i stop ? 65 115 a system in stop mode, microcontroller not clocked, wake capable via lin and mon; gpios open (no loads) or connected to gnd; t j = - 40c to 85c p_1.3.19 current consumption in stop mode i stop_v_exte nd ? 3.5 4.0 ma system in stop mode, microcontroller not clocked, wake capable via lin and mon; gpios open (no loads) or connected to gnd; t j = - 40c to 85c; v s =3v p_1.3.21 current consumption in stop mode with cyclic sense i stop_cs ? 70 125 a system in stop mode (during stop period), microcontroller not clocked, wake capable via lin and mon; vddext off; high side off; gpios open (no loads) or connected to gnd or vddp; t j = - 40c to 85c; v s = 5.5v to 28v p_1.3.20 1) not subject to production test, specified by design table 20 electrical characteristics (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 91 rev. 1.0, 2016-05-06 28.1.5 timing characteristics the transition times between the system modes are specified here. generally the timings are defined from the time when the corresponding bits in register pmcon0 are set until the sequence is terminated. table 21 thermal resistance parameter symbol values unit note / test condition number min. typ. max. junction to case r th(jc) ?6?k/w 1) measured to exposed pad 1) not subject to production test, specified by design. p_1.4.1 junction to ambient r th(ja) ?33?k/w 2) 2) according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board . board: 76.2x114.3x1.5mm3 with 2 inner copper layers (35m thick), with thermal via array under th e exposed pad contacting the first inner copper layer and 300mm2 cooling area on t he bottom layer (70m). p_1.4.2 table 22 system timing 1) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. wake-up over battery t start ? ? 1 ms battery ramp-up till mcu reset is released; vs > 3v and reset = ?1? p_1.5.1 sleep-exit t sleep - exit ? ? 1 ms rising/falling edge of any wake-up signal (lin, mon) till mcu software running p_1.5.2 sleep-entry t sleep - entry ?? 330s 2) 2) wake events during sleep-entry are stored and lead to wake-up after sleep mode is reached. p_1.5.3
TLE9843QX electrical characteristics data sheet 92 rev. 1.0, 2016-05-06 28.2 power management unit (pmu) this chapter includes all electrical characteristics of the power management unit 28.2.1 pmu input voltage vs 28.2.2 pmu i/o supply parameters vddp table 23 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. required decoupling capacitance c vs1 0.1 ? ? f 1) esr < 1 ? 1) only min. value is tested. p_2.1.12 required buffer capacitance for stability (load jumps) c vs2 10 ? ? f 2) 2) not subject to production test, specified by design. p_2.1.13 table 24 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) parameter symbol values unit note / test condition number min. typ. max. specified outp ut current i vddp 0?50ma 2) p_2.1.1 required decoupling capacitance c vddp1 0.47 ? ? f 3)4) esr < 1 ? p_2.1.2 required buffer capacitance for stability (load jumps) c vddp2 0.47 ? 1 f 4)5) p_2.1.3 output voltage including line and load regulation @ active mode v ddpout 4.9 5.0 5.1 v 6) i load < 90ma;vs > 5.5v p_2.1.4 output voltage including line and load regulation @ stop mode v ddpouts top 4.5 5.0 5.25 v 6) i load is only internal;vs > 5.5v p_2.1.5 output drop vs v ddpout ?50+400mv 7) i vddp = 50ma; v s = 3v; p_2.1.6 load regulation v vddplor -50 ? 50 mv 2 ... 90ma; c = c vddp1 +c vddp2 p_2.1.7 line regulation v vddplir -50 ? 50 mv v s = 5.5 ... 28v p_2.1.8 over voltage detection v ddpov 5.14 ? 5.4 v v s > 5.5v; overvoltage leads to supply_nmi p_2.1.9
TLE9843QX electrical characteristics data sheet 93 rev. 1.0, 2016-05-06 under voltage reset v ddpuv 2.55 2.7 2.8 v ? p_2.1.10 over current diagnostic i vddpoc 90 ? 200 ma current including vddc current consumption p_2.1.11 1) currents used in this table are positive but flowing out the pin vddp 2) specified output current for port supply and additional other external loads connec ted to vddp, excluding on-chip current consumption. 3) only min. value is tested. 4) the total capacitance on vddp must not exceed 2,2 f 5) not subject to production test, specified by design. 6) load current includes internal supply. 7) output drop for i vddp plus internal supply table 24 electrical characteristics (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 94 rev. 1.0, 2016-05-06 28.2.3 pmu core supply parameters vddc table 25 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. required decoupling capacitance c vddc1 0.1 ? ? f 1) esr < 1 ? 1) only min. value is tested. p_2.2.1 required buffer capacitance for stability (load jumps) c vddc2 0.33 ? 1 f 2) ? 2) not subject to production test, specified by design. p_2.2.2 output voltage including line regulation @ active mode/stop mode v ddcout 1.44 1.5 1.56 v i load < 40ma; with setting of vddc output voltage to 1.5v in stop mode p_2.2.3 load regulation v ddclor -50 ? 50 mv 2 ... 40ma; c = c vddc1 +c vddc2 p_2.2.4 line regulation v ddclir -25 ? 25 mv v s = 5.5 ... 28v p_2.2.5 over voltage detection v ddcov 1.58 ? 1.68 v overvoltage leads to supply_nmi p_2.2.6 under voltage reset v ddvuv 1.10 ? 1.19 v ? p_2.2.7 over current diagnostic i vddcoc 40 ? 80 ma ? p_2.2.8
TLE9843QX electrical characteristics data sheet 95 rev. 1.0, 2016-05-06 28.2.4 vddext voltage regulator 5.0v table 26 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) parameter symbol values unit note / test condition number min. typ. max. vddext regulator active mode specified outp ut current i vddext 0 ? 20 ma current flowing out of pin vddext p_2.3.1 required decoupling capacitance c vddext1 330 ? 1000 nf 2) esr < 1 ? p_2.3.2 required buffer capacitance for stability (load jumps) c vddext2 100 ? 1000 nf 3) p_2.3.3 output voltage including line and load regulation v ddext 4.9 5.0 5.1 v i load < 20ma;vs 5.5v p_2.3.4 output drop v s - v ddext 50 +400 mv i load <20ma; 3v < v s <5.0v p_2.3.5 load regulation v ddextlor -80 ? 20 mv 0.01 ... 20ma; c = c vddext1 +c vddext2 ; v s 5.5v p_2.3.6 line regulation v vddextlir -50 ? 50 mv v s = 5.5 ... 28v p_2.3.7 power supply ripple rejection p ssrvddext 50 ? ? db 3) v s = 13.5v; f=0 ... 1khz; v r =2vpp; 0 ... 20ma p_2.3.8 under voltage shutdown v vddextuv 1.55 1.9 2.2 v 4) p_2.3.9 over current limitation i vddextoc 100 250 380 ma 3) ? p_2.3.10 vddext output discharge resistance r vddext_dis chg 16 20 24 k ? ? p_2.3.11 vddext regulator low current mode specified outp ut current i vddext_lcm 0 ? 5 ma ? p_2.3.28 output voltage including line and load regulation - load 1 v ddext_lcm 1 4.6 5.0 5.1 v i load 5ma;vs 5.5v p_2.3.29 output drop - load 1 v s - v ddext_lcm 1 50 +300 mv i load 5ma; 3v < v s 5v; c = c vddext1 +c vddext2 p_2.3.30 load regulation - load 1 v ddextlor_ lcm1 -250 ? 250 mv 0 ... 5ma; c = c vddext1 +c vddext2 ; v s 5.5v p_2.3.31 line regulation - load 1 v vddextlir_ lcm1 -300 ? 300 mv i load 5ma; v s = 5.5 ... 28v p_2.3.32 power supply ripple rejection p ssrvddext _lcm 50 ? ? db 3) vs= 13.5v; f=0 ... 1khz; vr=2vpp; 0 ... 5ma p_2.3.33
TLE9843QX electrical characteristics data sheet 96 rev. 1.0, 2016-05-06 1) currents used in this table are positive but flowing out the pin vddext 2) only min. value is tested. 3) not subject to production test, specified by design. 4) when condition is met, the bit vddext_ctrl.vddext_uv_is will be set.
TLE9843QX electrical characteristics data sheet 97 rev. 1.0, 2016-05-06 28.2.5 vpre voltage regulator (pmu subblock) parameters the pmu vpre regulator acts as a supply of vddp and vddc voltage regulators. 28.2.5.1 load sharing of vpre regulator the figure below shows the load sharing concept of vpre regulator. figure 36 load sharing of vpre regulator table 27 functional range parameter symbol values unit note / test condition number min. typ. max. specified outp ut current i vpre ??90ma 1) 1) not subject to production test, specified by design. p_2.4.1 load _sharing _vpre.vsd vddp - 5v max. 90 ma vddc - 1.5v max. 40 ma vpre max. 90 ma vs vddp gnda (pin 43) vddc c vddc load sharing vpre c vddp gnda (pin 43) max. 50 ma max. 0 ma
TLE9843QX electrical characteristics data sheet 98 rev. 1.0, 2016-05-06 28.2.6 power down voltage regula tor (pmu subblock) parameters the pmu power down voltage regulator consists of two subblocks: ? power down pre regulator: vdd5vpd ? power down core regulator: vdd1v5_pd (supply used for gpudataxy registers) both regulators are used as purely internal supplies. the following table contains all relevant parameter: table 28 functional range parameter symbol values unit note / test condition number min. typ. max. power-on reset threshold v dd1v5_pd_ rstth 1.2 ? 1.5 v 1) i load = internal load connected to vdd1v5_pd 1) not subject to production test, specified by design p_2.5.1
TLE9843QX electrical characteristics data sheet 99 rev. 1.0, 2016-05-06 28.3 system clocks 28.3.1 electrical characteris tics oscillators and pll table 29 electrical characteristics system clocks v s = 5.5 v to 28 v,, t j = -40 c to +150 c, all voltages with respec t to ground, positive cu rrent flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. pmu oscillators (power management unit) frequency of lp_clk f lp_clk 17 20 23 mhz this clock is used at startup and can be used in case the pll fails p_3.1.1 frequency of lp_clk2 f lp_clk2 70 100 130 khz this clock is used for cyclic wake p_3.1.2 cgu oscillator (clock genera tion unit microcontroller) short term frequency deviation 1) f trimst -0.4% ? +0.4% mhz within any 100 ms, e.g. after synchronization to a lin frame (includes pll accumulated jitter value).assuption: t j is varying < 30c. p_3.1.3 absolute accuracy f trimabsa -1.49% ? +1.49% mhz including temperature& lifetime drift and supply variation p_3.1.4 cgu-osc start-up time t osc ??10s 2) startup time osc from sleep mode, power supply stable p_3.1.5 pll (clock generation unit microcontroller) 2) vco reference frequency range f ref 0.8 1 1.25 mhz p_3.1.25 vco frequency (tuning) range f vco 75 ? 160 mhz p_3.1.21 input frequency range f osc 4 ? 6 mhz see also specified limits for f vco and f ref resulting in restrictions for possible n divider settings p_3.1.6 xtal1 input freq. range f oschp 4 ? 6 mhz see also specified limits for f vco and f ref resulting in restrictions for possible n divider settings p_3.1.23 output freq. range f pll 15 ? 40 mhz see also specified limits for f vco and f ref resulting in restrictions for possible n divider settings p_3.1.7 free-running frequency f vcofree ? 34 ? mhz p_3.1.24
TLE9843QX electrical characteristics data sheet 100 rev. 1.0, 2016-05-06 28.3.2 external clock para meters xtal1, xtal2 input clock high/low time t high/low 10 ? ? ns p_3.1.8 peak period jitter t jp -500 ? 500 ps for k=2; this parameter value is only valid with the combination of an external quartz oscillator (e.g. 5 mhz) p_3.1.9 accumulated jitter with external oscillator jacc_ext ? ? 5 ns for k=2; this parameter value is only valid with the combination of an external quartz oscillator (e.g. 5 mhz). p_3.1.10 lock-in time t l ? ? 260 s this parameter represents the duration from module power-on to assertion of lock signal p_3.1.11 1) the typical oscillator frequency is 40 mhz 2) not subject to production test, specified by design. table 30 functional range v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) parameter symbol values unit note / test condition number min. typ. max. input voltage range limits for signal on xtal1 v ix1_sr -1.7 + v ddc ?1.7 v 2) p_3.2.1 input voltage (amplitude) on xtal1 v ax1_sr 0.3 x v ddc ?? v 3) peak-to-peak voltage p_3.2.2 xtal1 input current i il ??20a0v < v in < v ddi p_3.2.3 oscillator frequency f osc 4 ? 6 mhz clock signal p_3.2.4 oscillator frequency f osc 4 ? 6 mhz crystal or resonator p_3.2.5 high time t 1 _ vcobyp 6??ns 4)5) p_3.2.6 low time t 2 _ vcobyp 6??ns 4)5) ? p_3.2.7 rise time t 3 _ vcobyp ?88ns 4)5) ? p_3.2.8 fall time t 4 _ vcobyp ?88ns 4)5) ? p_3.2.9 high time t 1 _ pllnm 12 ? ? ns 5)6) ? p_3.2.10 table 29 electrical characteristics system clocks (cont?d) v s = 5.5 v to 28 v,, t j = -40 c to +150 c, all voltages with respec t to ground, positive cu rrent flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 101 rev. 1.0, 2016-05-06 low time t 2 _ pllnm 12 ? ? ns 5)6) ? p_3.2.11 rise time t 3 _ pllnm ?77ns 5)6) ? p_3.2.12 fall time t 4 _ pllnm ?77ns 5)6) ? p_3.2.13 1) not subject to production test, specified by design. 2) overload conditions must not occur on pin xtal1. 3) the amplitude voltage v ax1 refers to the offset voltage v off . this offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by v ix1 . 4) this performance is only valid for prescaler mode (vco bypass mode). 5) tested with rectangular signal with v in_low = 0v to v in_high = v ddc 6) this performance is only valid for pll normal mode. table 30 functional range (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 102 rev. 1.0, 2016-05-06 28.4 flash parameters this chapter includes the parameters for the 48 kbyte embedded flash module. 28.4.1 flash characteristics table 31 flash characteristics 1) v s = 5.5 v to 28 v,, t j = -40 c to +150 c, all voltages with respec t to ground, positive cu rrent flowing into pin (unless otherwise specified) 1) not subject for production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. programming time per 128 byte page t pr ?3 2) 2) programming and erase times depend on the internal flash clock source. the control state machine needs a few system clock cycles. the requirement is only rele vant for extremely low system frequencies. 3.5 ms 3v < v s < 28v p_4.1.1 erase time per sector/page t er ?4 2) 4.5 ms 3v < v s < 28v p_4.1.2 data retention time t ret 20 ? ? years 1,000 erase / program cycles p_4.1.3 data retention time t ret 50 ? ? years 1,000 erase / program cycles t j = 30c 3) 3) derived by extrapolation of lifetime tests. p_4.1.4 flash erase endurance for user sectors n er 30 ? ? kcycles data retention time 5 years p_4.1.5 flash erase endurance for security pages 4) 4) temperature: 25 c n sec 10 ? ? cycles data retention time 20 years p_4.1.6 drain disturb limit n dd 32 ? ? kcycles 5) 5) this parameter limits the number of subsequent programming operations within a physical sector without a given page in this sector being (re-)programmed. the drain disturb limit is applicable if wordline erase is used repeatedly. for normal sector erase/program cycles this limit will not be violated. for da ta sectors the integrated eeprom emulation firmware routines handle this limit automatically, for wordline er ases in code sectors (withou t eeprom emulation) it is recommended to execute a software based refresh, which ma y make use of the integrat ed random number generator nvmbrng to statistically start a refresh. p_4.1.7
TLE9843QX electrical characteristics data sheet 103 rev. 1.0, 2016-05-06 28.5 parallel ports (gpio) 28.5.1 description of keep and force current figure 37 pull-up/down device figure 38 pull-up keep and forced current pull-up-down.vsd pu device pd device p1.x p0.x keeper current keeper current pudsel \pudsel v ss v ddp logical ?1" undefined logical ?0" current_diag.vsd -i plk -i plf v ih -v ddp v il -v ddp u gpio i 7.5 kohm (equivalent) (1.5v / 200ua) *) 2.33 kohm (equivalent) (3.5v / 1.5ma) *) *) value for port 0 and 1, as example
TLE9843QX electrical characteristics data sheet 104 rev. 1.0, 2016-05-06 figure 39 pull-down keep and force current 28.5.2 dc parameters port 0, port 1, tms, reset table 32 dc characteristics port0, port1 v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. input low voltage v il -0.3 ? 0.3 x v ddp v 1) 4.5v v ddp 5.5v p_5.2.1 input low voltage v il_extend -0.3 0.42 x v ddp ?v 2) 2.6v v ddp < 4.5v p_5.2.14 input high voltage v ih 0.7 x v ddp ? v ddp + 0.3 v 1) 4.5v v ddp 5.5v p_5.2.2 input high voltage v ih_extend ? 0.52 x v ddp v ddp + 0.3 v 2) 2.6v v ddp < 4.5v p_5.2.15 input hysteresis hys 0.11 x v ddp ?? v 2) 4.5v v ddp 5.5v; series resistance = 0 ? p_5.2.3 input hysteresis hys extend ? 0.09 x v ddp ?v 2) 2.6v v ddp < 4.5v; series resistance = 0 ? p_5.2.16 output low voltage v ol ??1.0v 3) 4) i ol i olmax p_5.2.4 output low voltage v ol ??0.4v 3) 5) iol iolnom p_5.2.5 output high voltage v oh v ddp - 1.0 ? ? v 3) 4) i oh i ohmax p_5.2.6 output high voltage v oh v ddp - 0.4 ? ? v 3) 5) i oh i ohnom p_5.2.7 input leakage current i oz2 -5 ? +5 a 6) t j 85c, 0.45 v < v in < v ddp p_5.2.8 logical ?1" undefined logical ?0" current_diag-pull _down.vsd i plk i plf i 2.33 kohm (equivalent) (3.5v / 1.5ma) *) 7.5 kohm (equivalent ) (1.5v / 200ua) *) u gpio v ih v il *) value for port 0 and 1, as example
TLE9843QX electrical characteristics data sheet 105 rev. 1.0, 2016-05-06 note: operating conditions apply. keeping signal levels within the limits specified in th is table ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . input leakage current i oz2 -15 ? +15 a t j 150c, 0.45 v < v in < v ddp p_5.2.9 pull level keep current 7) i plk ? ? 200 a 8) v pin v ih (up) v pin v il (dn) p_5.2.10 pull level force current 7) i plf 1.5 ? ? ma 8) v pin v il (up) v pin v ih (dn) p_5.2.11 pin capacitance c io ??10pf 2) p_5.2.12 reset pin timing reset pin input filter time t filt_reset ?5?s 9) p_5.2.13 1) tested at v ddp = 5v, specified for 2.55v < v ddp < 5.1v. 2) not subject to production test, specified by design. 3) the maximum deliverable output current of a port driver dep ends on the selected output dr iver mode. the limit for pin groups must be respected. 4) tested at 2.55v < v ddp < 5.1v, i ol = 4ma, i oh = -4ma, specified for 2.7v < v ddp < 5.1v. 5) as a rule, with decreasing output current the output levels approac h the respective supply level ( v ol gnd , v oh v ddp ). tested at 2.55v < v ddp < 5.1v, i ol = 1ma, i oh = -1ma. 6) the given values are worst-case values. in production test, th is leakage current is only te sted at 125c; other values are ensured by correlation. for derating, please refer to the following descriptions: leakage derating depending on temperature ( t j = junction temperature [c]): i oz = 0.05 e (1.5 + 0.028tj) [ a]. for example, at a temperature of 95 c the resulting leakage current is 3.2 a. leakage derating depending on voltage level (dv = v ddp - v pin [v]): i oz = i oztempmax - (1.6 dv) [ a] this voltage derating formula is an approxim ation which applies for maximum temperature. 7) negative current is representing pullup; positive current is representing pulldown 8) keep current: limit the current through this pin to the indi cated value so that the enabled pull device can keep the default pin level: v pin v ih for a pull-up; v pin v il for a pull-down. force current: drive the indicat ed minimum current through this pin to change the default pin level driven by the enabled pull device: v pin v il for a pull-up; v pin v ih for a pull-down. these values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose io pins. 9) this filter time and its variation is derived from the time base t lp_clk = 1 / f lp_clk . table 33 current limits fo r port output drivers 1) port output driver mode maximum output current ( i olmax , - i ohmax ) output current ( i olnom , - i ohnom ) number vddp 4.5v 2.55v < vddp < 4.5v vddp 4.5v 2.55v < vddp < 4.5v strong driver 5 ma 3 ma 1.6 ma 1.0 ma p_5.2.20 table 32 dc characteristics port0, port1 (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 106 rev. 1.0, 2016-05-06 28.5.3 dc parameters port 2 these parameters apply to the io voltage range, 2.55 v v ddp 5.5 v. note: operating conditions apply. keeping signal levels within the limits specified in th is table ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . medium driver 3 ma 1.8 ma 1.0 ma 0.8 ma p_5.2.21 weak driver 0.5 ma 0.3 ma 0.25 ma 0.15 ma p_5.2.22 1) not subject to production test, specified by design. table 34 dc characteristics port 2 v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. input low voltage v il_p2 -0.3 ? 0.3 x v ddp v 1) 4.5v v ddp 5.5v p_5.3.1 input low voltage v il_p2_exte nd -0.3 0.42 x v ddp ?v 2) 2.6v v ddp < 4.5v p_5.3.8 input high voltage v ih_p2 0.7 x v ddp ? v ddp + 0.3 v 1) 4.5v v ddp 5.5v p_5.3.2 input high voltage v ih_p2_ext end ? 0.52 x v ddp v ddp + 0.3 v 2) 2.6v v ddp < 4.5v p_5.3.9 input hysteresis hys p2 0.11 x v ddp ?? v 2) 4.5v v ddp 5.5v; series resistance = 0 ? p_5.3.3 input hysteresis hys p2_ext end ? 0.09 x v ddp ?v 2) 2.6v v ddp < 4.5v; series resistance = 0 ? p_5.3.10 input leakage current i oz1_p2 -400 ? +400 na 4.5v v ddp 5.5v t j 85c, 0v < v in < v ddp p_5.3.4 input leakage current (extended temperature range) i oz1_p2_t_ extend -1 ? +1 ua 2.6v v ddp < 4.5v t j 150c, 0v < v in < v ddp p_5.3.11 pull level keep current 4) i plk_p2 ??30a 3) vpin vih (up) vpin vil (dn) p_5.3.5 table 33 current limits fo r port output drivers 1) (cont?d) port output driver mode maximum output current ( i olmax , - i ohmax ) output current ( i olnom , - i ohnom ) number vddp 4.5v 2.55v < vddp < 4.5v vddp 4.5v 2.55v < vddp < 4.5v
TLE9843QX electrical characteristics data sheet 107 rev. 1.0, 2016-05-06 28.5.4 operating conditions the following operating conditions must not be exceeded to ensure correct operation of the TLE9843QX. all parameters specified in th e following sections refer to these operat ing conditions, unless otherwise noticed. note: typical parameter values refer to room temperature and nominal supply voltage, minimum/maximum parameter values also include conditions of minimum/maximum temperature and minimum/maximum supply volt age. additional details are described where applicable. pull level force current 4) i plf_p2 750 ? ? a 3) vpin vil (up) vpin vih (dn) p_5.3.6 pin capacitance (digital inputs/outputs) c io_p2 ??10pf 2) p_5.3.7 1) tested at v ddp = 5v, specified for 4.9v < v ddp < 5.1v. 2) not subject to production test, specified by design. 3) keep current: limit the current through this pin to the indi cated value so that the enabled pull device can keep the default pin level: v pin v ih for a pull-up; v pin v il for a pull-down. force current: drive the indicat ed minimum current through this pin to change the default pin level driven by the enabled pull device: v pin v il for a pull-up; v pin v ih for a pull-down. 4) negative current is representing pullup; positive current is representing pulldown table 35 operating condition parameters v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. digital core supply voltage v ddc 1.35 ? 1.6 v full active mode p_5.4.1 digital supply voltage for io pads v ddp 2.55 5.0 5.5 v 1) p_5.4.2 digital ground voltage v ss 0 ? 0 v reference voltage p_5.4.3 overload current i ov - 5.0 ? 5.0 ma per io pin 2)3) p_5.4.4 overload current i ov - 2.0 ? 5.0 ma per analog input pin 2)3) p_5.4.5 overload positive current coupling factor for analog inputs 4) k ova ?1.0 x10 -6 1.0 x10 -4 ? i ov > 0 3) p_5.4.6 overload negative current coupling factor for analog inputs k ova ?2.5 x10 -4 1.5 x10 -3 ? i ov < 0 3) p_5.4.7 overload positive current coupling factor for digital i/o pins k ovd ?1.0 x10 -4 5.0 x10 -3 ? i ov > 0 3) p_5.4.8 overload negative current coupling factor for digital i/o pins k ovd ?1.0 x10 -2 3.0 x10 -2 ? i ov < 0 3) p_5.4.9 absolute sum of overload currents | i ov |? ? 80 ma 3) p_5.4.10 table 34 dc characteristics port 2 (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 108 rev. 1.0, 2016-05-06 1)performance of pad drivers, a/d converter, and flash module depends on v ddp . if the external supply voltage v ddp becomes lower than the specified operating range, a power reset must be generated. otherwise, the core supply voltage v ddi may rise above its specified operating range due to parasitic effects. this power reset can be generated by the on-chip swd. if the swd is disabled the po wer reset must be generated by activating the porst input 2) overload conditions occur if the standard operating conditi ons are exceeded, i.e. the voltage on any pin exceeds the specified range: v ov > v ihmax ( i ov >0) or v ov < v ilmin ( i ov < 0). the absolute sum of input overload currents on all pins may not exceed 50 ma . the supply voltages must remain wit hin the specified limits. proper op eration under overload conditions depends on the application. overload conditions must not occur on pin xtal1 (powered by v ddim ). 3) not subject to production test, specified by design. 4) an overload current ( i ov ) through a pin inject s an error current ( i inj ) into the adjacent pins. this error current adds to that pin?s leakage current ( i oz ). the value of the error current depends on the ov erload current and is defined by the overload coupling factor k ov . the polarity of the injected error current is reve rsed from the polarity of the overload current that produces it. the total current through a pin is | i tot | = | i oz | + (| i ov | x k ov ). the additional error current may distort the input voltage on analog inputs.
TLE9843QX electrical characteristics data sheet 109 rev. 1.0, 2016-05-06 28.6 lin transceiver 28.6.1 electrical characteristics table 36 electrical characteristics lin transceiver v s = 5.5v to 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. bus receiver interface receiver threshold voltage, recessive to dominant edge v th_dom 0.4 v s 0.45 v s 0.53 x v s v sae j2602 p_6.1.1 receiver dominant state v busdom -27 ? 0.4 v s v lin spec 2.2 (par. 17) p_6.1.2 receiver threshold voltage, dominant to recessive edge v th_rec 0.47 x v s 0.55 v s 0.6 v s v sae j2602 p_6.1.3 receiver recessive state v busrec 0.6 v s ?1.15 v s v 1) lin spec 2.2 (par. 18) p_6.1.4 receiver center voltage v bus_cn t 0.475 v s 0.5 v s 0.525 v s v 2) lin spec 2.2 (par. 19) p_6.1.5 receiver hysteresis v hys 0.07 v s 0.12 v s 0.175 v s v 3) lin spec 2.2 (par. 20) p_6.1.6 wake-up threshold voltage v bus,wk 0.4 v s 0.5 v s 0.6 v s v ? p_6.1.7 dominant time for bus wake- up t wk,bus 30 ? 150 s including analog and digital filter time. digital filter time can be adjusted by pmu.cnf_wake_fil ter p_6.1.8 bus transmitter interface bus recessive output voltage v bus,ro 0.8 v s ? v s v v txd = high level p_6.1.9 bus short circuit current i bus,sc 40 100 150 ma current limitation for driver dominant state driver on v bus = 18 v; lin spec 2.2 (par. 12) p_6.1.10 leakage current i bus_no_ gnd -1000 -450 0 a v s = 0 v; v bus = -12 v; lin spec 2.2 (par. 15) p_6.1.11 leakage current i bus_no_ bat ?1020 a v s = 0 v; v bus = 18 v; lin spec 2.2 (par. 16) p_6.1.12 leakage current i bus_pas _dom -1 ? ? ma v s = 18 v; v bus = 0 v; lin spec 2.2 (par. 13) p_6.1.13 leakage current i bus_pas _rec ?? 20 a v s = 8 v; v bus = 18 v; lin spec 2.2 (par. 14) p_6.1.14
TLE9843QX electrical characteristics data sheet 110 rev. 1.0, 2016-05-06 bus pull-up resistance r bus 20 30 47 k ? normal mode lin spec 2.2 (par. 26), also present in sleep mode p_6.1.15 ac characteristics - transceiver normal slope mode propagation delay bus dominant to rxd low t d(l),r 0.1 1 6 s lin spec 2.2 (param. 31) p_6.1.16 propagation delay bus recessive to rxd high t d(h),r 0.1 1 6 s lin spec 2.2 (param. 31) p_6.1.17 receiver delay symmetry t sym,r -2 ? 2 s t sym,r = t d(l),r - t d(h),r ; lin spec 2.2 (par. 32) p_6.1.18 duty cycle d1 normal slope mode (for worst case at 20 kbit/s) t duty1 0.396 ? ? 4) duty cycle 1 th rec (max) = 0.744 v s ; th dom (max) = 0.581 v s ; t bit = 50 s; d1 = t bus_rec(min) / 2 x t bit ; lin spec 2.2 (par. 27) p_6.1.19 duty cycle d2 normal slope mode (for worst case at 20 kbit/s) t duty2 ? ? 0.581 4) duty cycle 2 th rec (min) = 0.422 v s ; th dom (min) = 0.284 v s ; t bit = 50 s; d2 = t bus_rec(max) / 2 x t bit ; lin spec 2.2 (par. 28) p_6.1.20 ac characteristics - transceiver low slope mode propagation delay bus dominant to rxd low t d(l),r 0.1 1 6 s lin spec 2.2 (param. 31) p_6.1.21 propagation delay bus recessive to rxd high t d(h),r 0.1 1 6 s lin spec 2.2 (param. 31) p_6.1.22 receiver delay symmetry t sym,r -2 ? 2 s t sym,r = t d(l),r - t d(h),r ; lin spec 2.2 (par. 32) p_6.1.23 table 36 electrical characteristics lin transceiver (cont?d) v s = 5.5v to 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 111 rev. 1.0, 2016-05-06 duty cycle d3 (for worst case at 10,4 kbit/s) t duty1 0.417 ? ? 4) duty cycle 3 th rec (max) = 0.778 v s ; th dom (max) = 0.616 v s ; t bit = 96 s; d3 = t bus_rec(min) / 2 x t bit ; lin spec 2.2 (par. 29) p_6.1.24 duty cycle d4 (for worst case at 10,4 kbit/s) t duty2 ? ? 0.590 4) duty cycle 4 th rec (min) = 0.389 v s ; th dom (min) = 0.251 v s ; t bit = 96 s; d4 = t bus_rec(max) / 2 x t bit ; lin spec 2.2 (par. 30) p_6.1.25 ac characteristics - transceiver fast slope mode propagation delay bus dominant to rxd low t d(l),r 0.1 1 6 s ? p_6.1.26 propagation delay bus recessive to rxd high t d(h),r 0.1 1 6 s ? p_6.1.27 receiver delay symmetry- extended supply voltage range t sym,r -2.0 ? 2.0 s t sym,r = t d(l),r - t d(h),r ;p_6.1.42 duty cycle d5 (used for 62,5 kbit/s) t duty1 0.395 ? ? 4) duty cycle 5 th rec (max) = 0.744 v s ; th dom (max) = 0.581 v s ; t bit = 16s; d5 = t bus_rec(min) / 2 x t bit ; p_6.1.29 duty cycle d6 (used for 62,5 kbit/s) t duty2 ? ? 0.581 4) duty cycle 6 th rec (min)= 0.422 v s ; th dom (min)= 0.284 v s ; t bit = 16 s; d6 = t bus_rec(max) / 2 x t bit ; p_6.1.30 ac characteristics - flash mode propagation delay bus dominant to rxd low t d(l),r 0.1 0.5 6 s ? p_6.1.31 propagation delay bus recessive to rxd high t d(h),r 0.1 0.5 6 s ? p_6.1.32 receiver delay symmetry t sym,r -1.0 ? 2.0 s t sym,r = t d(l),r - t d(^h),r ;p_6.1.44 table 36 electrical characteristics lin transceiver (cont?d) v s = 5.5v to 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 112 rev. 1.0, 2016-05-06 duty cycle d7 (for worst case at 115 kbit/s) for +1 s receiver delay symmetry (used for 250 kbit/s programming) t duty1 0.395 ? ? 5) duty cycle d7 th rec (max) = 0.744 v s ; th dom (max) = 0.581 v s ; t bit = 8.7 s; d7 = t bus_rec(min) / 2 x t bit ; p_6.1.34 duty cycle d8 (for worst case at 115 kbit/s) for +1 s receiver delay symmetry (used for 250 kbit/s programming) t duty2 ? ? 0.578 5) duty cycle d8 th rec (min) = 0.422 v s ; th dom (min) = 0.284 v s ; t bit = 8.7 s; d8 = t bus_rec(max) / 2 x t bit ; p_6.1.35 lin input capacity c lin_in ?1530 pf 6) p_6.1.36 txd dominant time out t timeout 61220 ms v txd = 0 v p_6.1.37 thermal shutdown (junction temperature) thermal shutdown temp. t jsd 160 180 200 c 6) p_6.1.38 thermal shutdown hyst. ? t ?10? k 6) p_6.1.39 1) maximum limit specified by design. 2) v bus_cnt = ( v th_dom + v th rec )/2 3) v hys = v busrec - v busdom 4) bus load concerning lin spec 2.2: load 1 = 1 nf / 1 k ? = c bus / r bus load 2 = 6.8 nf / 660 ? = c bus / r bus load 3 = 10 nf / 500 ? = c bus / r bus 5) bus load load 1 = 1 nf / 500 ? = c bus / r bus 6) not subject to production test, specified by design. table 36 electrical characteristics lin transceiver (cont?d) v s = 5.5v to 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 113 rev. 1.0, 2016-05-06 28.7 high-speed synchr onous serial interface 28.7.1 ssc timing the table below provides the ssc timing in the TLE9843QX. figure 40 ssc master mode timing table 37 ssc master mode timing (o perating conditions apply; cl = 50 pf) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. sclk clock period t 0 1) 2 * t ssc 1) t sscmin =t cpu =1/ f cpu . if f cpu = 20 mhz, t 0 = 100 ns. t cpu is the cpu clock period. ?? 2) v ddp > 2.7 v 2) not subject to production test, specified by design. p_7.1.1 mtsr delay from sclk t 1 10 ??ns 2) v ddp > 2.7 v p_7.1.2 mrst setup to sclk t 2 10 ??ns 2) v ddp > 2.7 v p_7.1.3 mrst hold from sclk t 3 15 ??ns 2) v ddp > 2.7 v p_7.1.4 ssc_tmg1 sclk 1) mtsr 1) t 1 t 1 mrst 1) t 3 data valid t 2 t 1 1) this timing is based on the following setup: con.ph = con.po = 0. t 0
TLE9843QX electrical characteristics data sheet 114 rev. 1.0, 2016-05-06 28.8 measurement unit 28.8.1 electrical characteristics table 38 supply voltage signal conditioning v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. adc1 - battery / supply voltage measurement v bat_sense / v s input to output voltage attenuation: v bat_sense / v s att vbat_sense , att vs ? 0.047 ? p_8.1.10 nominal operating input voltage range v bat_sense / v s v bat_sense, range , v s, range 0? 25.7 7 v 2) max. value corresponds to typ. adc full scale input; p_8.1.11 accuracy of v bat_sense / v s after calibration - with iir filter ? v bat_sense_ii r , v s_iir -200 ? 200 mv v s = 5.5v to 18v, t j = -40..125c, f adci = f sys_max adc1_filtcoeff0_11. chx = 11?b. p_8.1.12 accuracy of v bat_sense / v s after calibration ? v bat_sense , v s -300 ? 300 mv v s = 5.5v to 18v, t j = -40..125c, f adci = f sys_max . p_8.1.36 adc1 - monitoring input voltage measurement v monx input to output voltage attenuation: vmonx att vmonx ? 0.039 ? p_8.1.13 nominal operating input voltage range vmonx v monx,range 0 ? 31.0 5 v 2) max. value corresponds to typ. adc full scale input; p_8.1.14 accuracy of v monx sense after calibration - with iir filter ? v monx_iir -241 ? 241 mv v s = 5.5v to 18v, t j = -40..125c, f adci = f sys_max adc1_filtcoeff0_11. chx = 11?b. p_8.1.33 accuracy of v monx sense after calibration - reduced operating range - with iir filter ? v monx_ror_iir -170 ? 170 mv 2) v s = 5.5v to 18v, t j = -40..125c, v monx,range = 0v to 12v, f adci = f sys_max , adc1_filtcoeff0_11. chx = 11?b. p_8.1.20
TLE9843QX electrical characteristics data sheet 115 rev. 1.0, 2016-05-06 accuracy of v monx sense after calibration ? v monx -361 ? 361 mv 2) v s = 5.5v to 18v, t j = -40..125c, f adci = f sys_max . p_8.1.37 adc1 - port 2.x voltage measurement v 2.x input to output voltage attenuation: vport2.x att 2.x ? 0.219 ? ? p_8.1.15 nominal operating input voltage range vport2.x v port2.x,range 0 ? 5.53 1) v 2) max. value corresponds to typ. adc full scale input; p_8.1.16 accuracy of v port2.x sense after calibration - with iir filter ? v port2.x_iir -43 ? 43 mv v s = 5.5v to 18v, t j = -40..125c, f adci = f sys_max adc1_filtcoeff0_11. chx = 11?b. p_8.1.34 accuracy of v port2.x sense after calibration ? v port2.x -67 ? 67 mv v s = 5.5v to 18v, t j = -40..125c, f adci = f sys_max . p_8.1.38 adc2 - supply voltage measurement v s input to output voltage attenuation: v s att vs_adc2 ? 0.039 ? p_8.1.1 nominal operating input voltage range v s v s,adc2 3 ? 31.0 5 v 2) max. value corresponds to typ. adc full scale input; 3v < v s < 28v p_8.1.2 accuracy of v s after calibration ? v s,adc2 -270 ? 270 mv v s = 5.5v to 18v, t j = -40..125c p_8.1.3 adc2 - vddext voltage measurement v ddext input to output voltage attenuation: vddext att vddext ? 0.203 ? ? p_8.1.17 nominal operating input voltage range vddext v ddext,range 0? 5.96v 2) max. value corresponds to typ. adc full scale input; p_8.1.18 adc2 - pad supply voltage measurement v vddp input-to-output voltage attenuation: vddp att vddp ? 0.203 ? ? p_8.1.4 nominal operating input voltage range vddp v ddp,range 0? 5.96v 2) max. value corresponds to typ. adc full scale input; p_8.1.5 table 38 supply voltage signal conditioning (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 116 rev. 1.0, 2016-05-06 adc2 - reference voltage measurement v bg input-to-output voltage attenuation: vbg att vbg ? 0.75 ? ? p_8.1.6 nominal operating input voltage range vbg v bg,range 0.8 ? vdd c - 0.1v v 2) max. value corresponds to typ. adc full scale input; p_8.1.7 value of adc2- v bg measurement after calibration v bg_pmu 0.90 1.0 1.1 v ? p_8.1.39 adc2 - core supply voltage measurement v ddc input-to-output voltage attenuation: vddc att vddc ? 0.75 ? ? p_8.1.8 nominal operating input voltage range vddc v ddc,range 0.6 ? vdd c + 0.1v v 2) max. value corresponds to typ. adc full scale input; p_8.1.9 1) this typical theoretical full scale is not reached as the internal esd clamping st ructure limits the voltage to max. 5.2v. 2) not subject to production test, specified by design. table 38 supply voltage signal conditioning (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 117 rev. 1.0, 2016-05-06 28.8.2 central temperature sensor module 28.8.2.1 electrical characteristics table 39 electrical characteristics temperature sensor module v s = 5.5 v to 28 v, , t j = -40 c to +150 c; all voltages with respec t to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output voltage v temp at t 0 =0c (273 k) 2) a ? 0.628 ? v t 0 =0c (273 k) p_8.2.1 temperature sensitivity b 2) b ? 2.31 ? mv/k p_8.2.2 accuracy_1 acc_1 -10 ? 10 c 1) -40c < t j < 85c 1) accuracy with reference to on-chip temperature calibration measurement. p_8.2.3 accuracy_2 acc_2 -15 ? 15 c 125c < t j < 175c p_8.2.4 accuracy_3 acc_3 -5 ? 5 c 2) 85c < t j < 125c 2) not subject to production test, specified by design. p_8.2.5
TLE9843QX electrical characteristics data sheet 118 rev. 1.0, 2016-05-06 28.9 adc1 (10-bit) 28.9.1 adc1 reference voltage 28.9.2 electrical charact eristics adc1 (10-bit) these parameters describe the conditions for optimum adc performance. note: operating conditions apply. table 40 dc specifications v s = 5.5 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. reference voltage v bg -1% 1.211 +1% v p_9.1.10 temperature drift ? v bg -1% +1% v p_9.1.11 table 41 a/d converter characteristics v s = 5.5 v to 28 v, , t j = -40 c to +150 c; all voltages with respec t to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. analog clock frequency f adci 5?40mhz 1) p_9.2.1 dnl error ea dnl ?? 2lsb 2) ? p_9.2.8 inl error ea inl ? ? 3 lsb ? p_9.2.9 gain error ea gain ?? 1.2% of fsr 3) 4) calibrated; gain error is calibrated by implemented calibration unit p_9.2.10 offset error ea off ?? 2.5lsb 4) calibrated; offset error is calibrated by implemented calibration unit p_9.2.11 total unadjusted error ea tue ? ? 10 lsb already calibrated p_9.2.33
TLE9843QX electrical characteristics data sheet 119 rev. 1.0, 2016-05-06 input referred noise v noise_lsb ??1.5lsb rms 4) t j = 25c; this value is determined out of 4 consecutive measurements which are averaged. p_9.2.34 cross-coupling attenuation between lv channels ea ccoup ?1 2lsb 4) ? p_9.2.12 input capacitance of a hv analog input c aint_hvi ??200ff 4) p_9.2.13 input capacitance of a lv analog input c aint_lvi ??200ff 4) p_9.2.19 1) the limit values for f adci must not be exceeded when selecting the peripheral frequency and the prescaler setting. 2) this parameter is measured with disabled hardware calibration 3) this gain error is calibrated by ifx end of line 4) not subject to production test table 41 a/d converter characteristics (cont?d) v s = 5.5 v to 28 v, , t j = -40 c to +150 c; all voltages with respec t to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 120 rev. 1.0, 2016-05-06 28.10 high-voltage monitoring input 28.10.1 electrical characteristics table 42 electrical characteristics monitoring input v s = 5.5 v to 28 v; t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. mon input pin characteristics wake-up/monitoring threshold voltage v month 0.4*v s 0.5*v s 0.6*v s v without external serial resistor r s (with r s :dv = i pd/pu * r s ); p_10.1.1 threshold hysteresis v month,hys 0.015* v s 0.06*v s 0.10*v s v in all modes; without external serial resistor r s (with r s :dv = i pd/pu * r s ); 5.5 v < v s < 18 v p_10.1.2 threshold hysteresis- extended supply voltage range v month,hys _vs_extende d 0.02*v s 0.06*v s 0.12*v s v in all modes; without external serial resistor r s (with r s :dv = i pd/pu * r s ); 18 v < v s < 28 v p_10.1.7 pull-up current i pu, mon -20 -10 -5 a 0.6*v s ; p_10.1.3 pull-down current i pd, mon 51020a0.4*v s ; p_10.1.4 input leakage current i lk,mon -2 ? 2 a 0 v < v mon_in < 28 v p_10.1.5 timing wake-up filter time t ft,mon -20-s 1) 1) with pull-up, pull down current disabled. p_10.1.6
TLE9843QX electrical characteristics data sheet 121 rev. 1.0, 2016-05-06 28.11 high side switches 28.11.1 electrical characteristics table 43 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. pwm frequency of hs with slew rate control f pwm_w_sr 0?10khz 1) frequency must be configured in the pwm generator p_11.1.1 pwm frequency of hs without slew rate control f pwm_w/o_sr 0?25 2) khz 1) frequency must be configured in the pwm generator p_11.1.2 output hs on-state resistance r on 21018 ? 5.5 v < v s < 28v, ids=100ma, t j = 25 c p_11.1.3 output leakage current i leakage ? ? 2 a output off 0 v < v xlo < v s ; t j 150 c p_11.1.4 output slew rate (rising) with slow slew rate setting (slew rate 1) sr raise_sr1 1 ? 10 v/s 20% to 80% of v s v s = 9 to 18v r l =300 ? 1) p_11.1.5 output slew rate (falling) with slow slew rate setting (slew rate 1) sr fall_sr1 -10 ? -1 v/s 80% to 20% of v s v s = 9 to 18v r l =300 ? 1) p_11.1.6 output slew rate (rising) with fast slew rate setting (slew rate 2) sr raise_sr2 18.0 ? 55.0 v/s 20% to 80% of v s v s = 9 to 18v r l =300 ? 1) p_11.1.7 output slew rate (falling) with fast slew rate setting (slew rate 2) sr fall_sr2 -43.4 ? -12.5 v/s 80% to 20% of v s v s = 9 to 18v r l =300 ? 1) p_11.1.8 turn on delay time (slew rate 1) t in-hs_sr1 ? ? 4.5 s on = 1 to 20% of v s r l =300 ? p_11.1.9 turn on time (slew rate 1) t on_sr1 1 ?15s v s = 9 to 18v hs_on=1 to 80% of v s r l =300 ? t j =25c p_11.1.10 turn off time (slew rate 1) t off_sr1 1 ?15s v s = 9 to 18v hs_on= 0 to 20% of v s r l =300 ? ; t j =25c p_11.1.11
TLE9843QX electrical characteristics data sheet 122 rev. 1.0, 2016-05-06 turn on delay time (slew rate 2) t in-hs_sr2 ? ? 1 s on = 1 to 20% of v s r l =300 ? p_11.1.55 turn on time (slew rate 2) t on_sr2 ? ?3s v s = 9 to 18v hs_on=1 to 80% of v s r l =300 ? t j =25c p_11.1.56 turn off time (slew rate 2) t off_sr2 ? ?3s v s = 9 to 18v hs_on= 0 to 20% of v s r l =300 ? ; t j =25c p_11.1.57 over-current detection overcurrent threshold 0 i octh0 26 42 60 ma v s = 13.5v hsx_oc_sel =00 p_11.1.12 overcurrent threshold 0 hysteresis i octh0,hyst ?14?ma 1) hsx_oc_sel =00 p_11.1.13 overcurrent threshold 1 i octh1 51 60 80 ma v s = 13.5v hsx_oc_sel =01 p_11.1.14 overcurrent threshold 1 hysteresis i octh1,hyst ?17?ma 1) hsx_oc_sel =01 p_11.1.15 overcurrent threshold 2 i octh2 101 123 150 ma v s = 13.5v hsx_oc_sel =10 p_11.1.16 overcurrent threshold 2 hysteresis i octh2,hyst ?25?ma 1) hsx_oc_sel =10 p_11.1.17 overcurrent threshold 3 i octh3 151 176 210 ma v s = 13.5v hsx_oc_sel =11 p_11.1.18 overcurrent threshold 3 hysteresis i octh3,hyst ?30?ma 1) hsx_oc_sel =11 p_11.1.19 over-current shutdown response time t ocft 8?80s 1) vs = 13.5v, r l =100 ? , hs_on to oc_sd (including switch- on time) p_11.1.20 on-state open load detection open load threshold i olonth 0.46 1.32 2.2 ma ? p_11.1.21 hysteresis i olonhys 35 155 300 a ? p_11.1.22 cyclic sense mode current capability i hs max sleep_pd 40 ? ? ma sleep mode / stop mode p_11.1.23 on-state resistance r on,static ??40 ? ids = 40ma, p_11.1.24 table 43 electrical characteristics (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 123 rev. 1.0, 2016-05-06 output slew rate (rising) sr rise_cyc 1 ? ? v/s 20% to 80% of v s v s = 9 to 18v r l =300 ? p_11.1.25 output slew rate (falling) sr fal_cycl ? ? -1 v/s 80% to 20% of v s v s = 9 to 18v r l =300 ? p_11.1.26 delay time cyclic_on-hs t in_cyc ? ? 2 s on =1 to 20% of v s rl=300 ? p_11.1.27 turn-on time t on_cyc ??15s v s = 9 to 18v on=1 to 80% r l =300 ? p_11.1.28 turn-off time t off_cyc ??15s v s = 9 to 18v on=0 to 20% of v s r l =300 ? ; t j =25c p_11.1.29 1) not subject to production test, specified by design. 2) this is an additional requirement which refers to a 47oh m series resistor to charge an external power mos gate. table 43 electrical characteristics (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9843QX electrical characteristics data sheet 124 rev. 1.0, 2016-05-06 28.12 low side switches 28.12.1 electrical characteristics table 44 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. pwm frequency of ls f pwm ??25khz 1) r l =270 ? p_12.1.1 overcurrent limitation i lstyp 270 300 330 ma p_12.1.2 on-state resistance r on 1410 ? i ds =100ma; p_12.1.3 leakage current i leakage ??2a0 v < v ls < v s ; t j < 85c p_12.1.5 turn on delay time, slow mode t don-ls ??50s 2) ls_on=1 to 0.9*vs v s =13.5v, r l =270 ? p_12.1.6 turn on delay time, pwm mode t don,f-ls ? ? 0.5 s ls_on=1 to 0.9*vs v s =13.5v, r l =270 ? p_12.1.7 turn on fall time, pwm mode t onf,pwm ?11.25s v ls 0.9*vs to 0.1*vs v s =13.5v, r l =270 ? p_12.1.8 turn on fall time, slow mode t onf,slow ? 100 150 s 2) vls 0.9*vs to 0.1*vs vs=13.5v, rl =270 ? p_12.1.9 turn off delay time, slow mode t doff-ls ??50s 2) ls_on=0 to 0.1*vs v s =13.5v, r l =270 ? p_12.1.10 turn off delay time, pwm mode t doff,f-ls ? ? 2 s ls_on=0 to 0.1*vs v s =13.5v, r l =270 ? p_12.1.11 turn off rise time, pwm mode t offr,pwm ?11.25s v ls 0.1*vs to 0.9*vs; v s =13.5v, r l =270 ? p_12.1.12 turn off rise time, slow mode t offr,slow ? 100 150 s 2) v ls 0.1*vs to 0.9*vs; v s =13.5v, r l =270 ? p_12.1.13 minimum duty cycle pulse width variation ton min 1.5 2 3.5 s ton(dig) = 2s 1) p_12.1.14 typical (systematic) pulse width increase ls_on to vls d ton typ ? 1.25 ? s ton(dig) = 2s 1) p_12.1.15 zener clamp voltage v az ? 50 ? v values are valid at t j = 25c p_12.1.16 clamping energy (repetitive) e clamp ??2mj 1)3) 1.000.000 cycles, @ i max = 90ma p_12.1.17 clamping energy e clamp ??14mj 1)3) 10 cycles, tstart = 25c, @ i max = 230ma p_12.1.18 clamping energy (single), hot e clamp ??7mj 1)3) 10 cycles, tstart = 85c, @ i max = 230ma p_12.1.19
TLE9843QX electrical characteristics data sheet 125 rev. 1.0, 2016-05-06 1) not subject to production test, specified by design. 2) static on mode (no pwm) 3) valid for one low-side, not for both at the same time
data sheet 126 rev. 1.0, 2016-05-06 TLE9843QX package outlines 29 package outlines figure 41 package outline vqfn-48-31 (with lti) notes 1. you can find all of our packages, sorts of packing an d others in our infineon internet page ?products?: http://www.infineon.com/products . 2. dimensions in mm. pg-vqfn-48-29, -31-po v05 7 0.1 a 6.8 7 0.1 b 11 x 0.5 = 5.5 0.5 0.5 0.07 0.1 0.05 0.13 0.05 0.26 0.15 0.05 (6) (5.2) 0.9 max. (0.65) +0.03 1) 2) 48x 0.08 (0.2) 0.05 max. c (5.2) (6) 0.1 0.03 0.05 0.23 m 48x 0.1 a b c 1) vertical burr 0.03 max., all sides 2) these four metal areas have exposed diepad potential index marking seating plane index marking 6.8 12 1 13 24 25 36 (0.35) 37 48 0.4 x 45
TLE9843QX revision history data sheet 127 rev. 1.0, 2016-05-06 30 revision history revision history page or item subjects (major changes since previous revision) rev. 1.0, 2016-05-06 initial revision
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